[llvm] r337442 - Fix spelling mistake in comments. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Jul 19 02:14:39 2018
New Revision: 337442

URL: http://llvm.org/viewvc/llvm-project?rev=337442&view=rev
Log:
Fix spelling mistake in comments. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=337442&r1=337441&r2=337442&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul 19 02:14:39 2018
@@ -724,7 +724,7 @@ let Predicates = [UseSSE1] in {
             (MOVLPSmr addr:$src1, VR128:$src2)>;
 
   // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
-  // end up with a movsd or bleand instead of shufp.
+  // end up with a movsd or blend instead of shufp.
   // No need for aligned load, we're only loading 64-bits.
   def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
             (MOVLPSrm VR128:$src1, addr:$src2)>;
@@ -780,7 +780,7 @@ let Predicates = [UseAVX] in {
 
 let Predicates = [UseSSE1] in {
   // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
-  // end up with a movsd or bleand instead of shufp.
+  // end up with a movsd or blend instead of shufp.
   // No need for aligned load, we're only loading 64-bits.
   def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
             (MOVHPSrm VR128:$src1, addr:$src2)>;