[PATCH] D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type

[Zixuan Wu via Phabricator via llvm-commits]

wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai.

To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding.
Use xxsel to match vselect if vsx is open, or use vsel.

In order to do not write many patterns in td file, promote(for vector it's bitcast) all other type into v4i32 and only pattern match vselect of v4i32 into vsel or xxsel


Repository:
  rL LLVM

https://reviews.llvm.org/D49531

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/vec_select.ll

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