[PATCH] D49524: Avoid generating FGETSIGN for f16

[Steve Canon via Phabricator via llvm-commits]

scanon created this revision.
scanon added a reviewer: ab.
Herald added a subscriber: llvm-commits.

Current SimplifyDemandedBits attempts to generate FGETSIGN from a bitcast of f16->i16 that only wants the signbit. That on its own is fine, except that we end up producing a bad shift node downstream. If we fix *that*, we'll run into issues legalizing the FGETSIGN in such a way that we don't end up right back with a bitcast followed by a shift, which is what we started with.

So. Instead simply skip out if we have a f16, which is the same thing we do for f128. This maybe isn't ideal, but it fixes the immediate problem (a crash) and a long-term right fix is somewhat non-obvious, so this will do fine.


Repository:
  rL LLVM

https://reviews.llvm.org/D49524

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1187,6 +1187,7 @@
       bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
       bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
       if ((OpVTLegal || i32Legal) && VT.isSimple() &&
+           Op.getOperand(0).getValueType() != MVT::f16 &&
            Op.getOperand(0).getValueType() != MVT::f128) {
         // Cannot eliminate/lower SHL for f128 yet.
         EVT Ty = OpVTLegal ? VT : MVT::i32;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D49524.156182.patch
Type: text/x-patch
Size: 653 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180718/9c097e04/attachment.bin>