[llvm] r337383 - [AArch64][SVE] Asm: Support for unpredicated FP operations.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 18 04:59:12 PDT 2018
Author: s.desmalen
Date: Wed Jul 18 04:59:12 2018
New Revision: 337383
URL: http://llvm.org/viewvc/llvm-project?rev=337383&view=rev
Log:
[AArch64][SVE] Asm: Support for unpredicated FP operations.
This patch adds support for the following unpredicated
floating-point instructions:
FADD Floating point add
FSUB Floating point subtract
FMUL Floating point multiplication
FTSMUL Floating point trigonometric starting value
FRECPS Floating point reciprocal step
FRSQRTS Floating point reciprocal square root step
The instructions have the following assembly format:
fadd z0.h, z1.h, z2.h
and have variants for 16, 32 and 64-bit FP elements.
Added:
llvm/trunk/test/MC/AArch64/SVE/frecps-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/frecps.s
llvm/trunk/test/MC/AArch64/SVE/frsqrts-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/frsqrts.s
llvm/trunk/test/MC/AArch64/SVE/ftsmul-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ftsmul.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/fadd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fadd.s
llvm/trunk/test/MC/AArch64/SVE/fmul-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fmul.s
llvm/trunk/test/MC/AArch64/SVE/fsub-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fsub.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed Jul 18 04:59:12 2018
@@ -125,6 +125,13 @@ let Predicates = [HasSVE] in {
defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">;
defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">;
+ defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd">;
+ defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub">;
+ defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">;
+ defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul">;
+ defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">;
+ defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">;
+
defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed Jul 18 04:59:12 2018
@@ -987,6 +987,34 @@ multiclass sve_fp_2op_p_zds<bits<4> opc,
//===----------------------------------------------------------------------===//
+// SVE Floating Point Arithmetic - Unpredicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm,
+ ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
+ asm, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zm;
+ bits<5> Zn;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Zm;
+ let Inst{15-13} = 0b000;
+ let Inst{12-10} = opc;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve_fp_3op_u_zd<bits<3> opc, string asm> {
+ def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>;
+ def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>;
+ def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
// SVE Floating Point Fused Multiply-Add Group
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/AArch64/SVE/fadd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fadd-diagnostics.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fadd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fadd-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -51,6 +51,15 @@ fadd z0.h, p7/m, z0.h, z31.s
// CHECK-NEXT: fadd z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fadd z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fadd z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadd z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fadd z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
Modified: llvm/trunk/test/MC/AArch64/SVE/fadd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fadd.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fadd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fadd.s Wed Jul 18 04:59:12 2018
@@ -72,3 +72,21 @@ fadd z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c0 65 <unknown>
+
+fadd z0.h, z1.h, z31.h
+// CHECK-INST: fadd z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x00,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 5f 65 <unknown>
+
+fadd z0.s, z1.s, z31.s
+// CHECK-INST: fadd z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x00,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 9f 65 <unknown>
+
+fadd z0.d, z1.d, z31.d
+// CHECK-INST: fadd z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x00,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 df 65 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/fmul-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fmul-diagnostics.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fmul-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fmul-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -43,17 +43,17 @@ fmul z0.h, z0.h, z8.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmul z0.h, z0.h, z8.h[0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmul z0.h, z0.h, z8.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmul z0.s, z0.s, z8.s[0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmul z0.s, z0.s, z8.s[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fmul z0.d, z0.d, z16.d[0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmul z0.d, z0.d, z16.d[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
@@ -114,6 +114,16 @@ fmul z0.h, p7/m, z0.h, z31.s
// CHECK-NEXT: fmul z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fmul z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmul z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmul z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fmul z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Invalid predicate
Modified: llvm/trunk/test/MC/AArch64/SVE/fmul.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fmul.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fmul.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fmul.s Wed Jul 18 04:59:12 2018
@@ -102,3 +102,21 @@ fmul z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
+
+fmul z0.h, z1.h, z31.h
+// CHECK-INST: fmul z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x08,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 08 5f 65 <unknown>
+
+fmul z0.s, z1.s, z31.s
+// CHECK-INST: fmul z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x08,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 08 9f 65 <unknown>
+
+fmul z0.d, z1.d, z31.d
+// CHECK-INST: fmul z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x08,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 08 df 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/frecps-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/frecps-diagnostics.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/frecps-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/frecps-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+frecps z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frecps z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frecps z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frecps z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/frecps.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/frecps.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/frecps.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/frecps.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+frecps z0.h, z1.h, z31.h
+// CHECK-INST: frecps z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x18,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 18 5f 65 <unknown>
+
+frecps z0.s, z1.s, z31.s
+// CHECK-INST: frecps z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x18,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 18 9f 65 <unknown>
+
+frecps z0.d, z1.d, z31.d
+// CHECK-INST: frecps z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x18,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 18 df 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/frsqrts-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/frsqrts-diagnostics.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/frsqrts-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/frsqrts-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+frsqrts z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frsqrts z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frsqrts z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frsqrts z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/frsqrts.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/frsqrts.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/frsqrts.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/frsqrts.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+frsqrts z0.h, z1.h, z31.h
+// CHECK-INST: frsqrts z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x1c,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c 5f 65 <unknown>
+
+frsqrts z0.s, z1.s, z31.s
+// CHECK-INST: frsqrts z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x1c,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c 9f 65 <unknown>
+
+frsqrts z0.d, z1.d, z31.d
+// CHECK-INST: frsqrts z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x1c,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 1c df 65 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/fsub-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fsub-diagnostics.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fsub-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fsub-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -51,6 +51,15 @@ fsub z0.h, p7/m, z0.h, z31.s
// CHECK-NEXT: fsub z0.h, p7/m, z0.h, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fsub z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsub z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fsub z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fsub z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
Modified: llvm/trunk/test/MC/AArch64/SVE/fsub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fsub.s?rev=337383&r1=337382&r2=337383&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fsub.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fsub.s Wed Jul 18 04:59:12 2018
@@ -72,3 +72,21 @@ fsub z0.d, p7/m, z0.d, z31.d
// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 9f c1 65 <unknown>
+
+fsub z0.h, z1.h, z31.h
+// CHECK-INST: fsub z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x04,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 5f 65 <unknown>
+
+fsub z0.s, z1.s, z31.s
+// CHECK-INST: fsub z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x04,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 9f 65 <unknown>
+
+fsub z0.d, z1.d, z31.d
+// CHECK-INST: fsub z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x04,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 df 65 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ftsmul-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ftsmul-diagnostics.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ftsmul-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ftsmul-diagnostics.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,15 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+ftsmul z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ftsmul z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ftsmul z0.h, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ftsmul z0.h, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ftsmul.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ftsmul.s?rev=337383&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ftsmul.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ftsmul.s Wed Jul 18 04:59:12 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ftsmul z0.h, z1.h, z31.h
+// CHECK-INST: ftsmul z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x0c,0x5f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 0c 5f 65 <unknown>
+
+ftsmul z0.s, z1.s, z31.s
+// CHECK-INST: ftsmul z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x0c,0x9f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 0c 9f 65 <unknown>
+
+ftsmul z0.d, z1.d, z31.d
+// CHECK-INST: ftsmul z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0x0c,0xdf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 0c df 65 <unknown>
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