[llvm] r337380 - [TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.

[Andrea Di Biagio via llvm-commits]

Author: adibiagio
Date: Wed Jul 18 04:16:31 2018
New Revision: 337380

URL: http://llvm.org/viewvc/llvm-project?rev=337380&view=rev
Log:
[TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.

This should have been part of r337378. I forgot to svn add it before committing
the change.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrPredicate.td

Modified: llvm/trunk/include/llvm/Target/TargetInstrPredicate.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrPredicate.td?rev=337380&r1=337379&r2=337380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrPredicate.td (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrPredicate.td Wed Jul 18 04:16:31 2018
@@ -111,6 +111,9 @@ class CheckRegOperand<int Index, Registe
   Register Reg = R;
 }
 
+// Check if register operand at index `Index` is the invalid register.
+class CheckInvalidRegOperand<int Index> : MCOperandPredicate<Index>;
+
 // Check that the operand at position `Index` is immediate `Imm`.
 class CheckImmOperand<int Index, int Imm> : MCOperandPredicate<Index> {
   int ImmVal = Imm;