[llvm] r337369 - [AArch64][SVE] Asm: Integer divide instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 18 02:17:30 PDT 2018
Author: s.desmalen
Date: Wed Jul 18 02:17:29 2018
New Revision: 337369
URL: http://llvm.org/viewvc/llvm-project?rev=337369&view=rev
Log:
[AArch64][SVE] Asm: Integer divide instructions.
This patch adds the following predicated instructions:
UDIV Unsigned divide active elements
UDIVR Unsigned divide active elements, reverse form.
SDIV Signed divide active elements
SDIVR Signed divide active elements, reverse form.
e.g.
udiv z0.s, p0/m, z0.s, z1.s
(unsigned divide active elements in z0 by z1, store result in z0)
sdivr z0.s, p0/m, z0.s, z1.s
(signed divide active elements in z1 by z0, store result in z0)
Added:
llvm/trunk/test/MC/AArch64/SVE/sdiv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sdiv.s
llvm/trunk/test/MC/AArch64/SVE/sdivr-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sdivr.s
llvm/trunk/test/MC/AArch64/SVE/udiv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/udiv.s
llvm/trunk/test/MC/AArch64/SVE/udivr-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/udivr.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=337369&r1=337368&r2=337369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Wed Jul 18 02:17:29 2018
@@ -67,6 +67,11 @@ let Predicates = [HasSVE] in {
defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">;
defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">;
+ defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">;
+ defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">;
+ defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">;
+ defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">;
+
defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">;
defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">;
defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=337369&r1=337368&r2=337369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Wed Jul 18 02:17:29 2018
@@ -1387,6 +1387,12 @@ multiclass sve_int_bin_pred_arit_2<bits<
def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
}
+// Special case for divides which are not defined for 8b/16b elements.
+multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> {
+ def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
+ def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Integer Multiply-Add Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/sdiv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sdiv-diagnostics.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sdiv-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sdiv-diagnostics.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+sdiv z0.b, p7/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdiv z0.b, p7/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdiv z0.h, p7/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdiv z0.h, p7/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+sdiv z0.s, p7/m, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sdiv z0.s, p7/m, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+sdiv z0.s, p8/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sdiv z0.s, p8/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sdiv.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sdiv.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sdiv.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sdiv.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sdiv z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: sdiv z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x1f,0x94,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f 94 04 <unknown>
+
+sdiv z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f d4 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/sdivr-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sdivr-diagnostics.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sdivr-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sdivr-diagnostics.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+sdivr z0.b, p7/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdivr z0.b, p7/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdivr z0.h, p7/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdivr z0.h, p7/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+sdivr z0.s, p7/m, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sdivr z0.s, p7/m, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+sdivr z0.s, p8/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sdivr z0.s, p8/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/sdivr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sdivr.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sdivr.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/sdivr.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sdivr z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: sdivr z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x1f,0x96,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f 96 04 <unknown>
+
+sdivr z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f d6 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/udiv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/udiv-diagnostics.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/udiv-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/udiv-diagnostics.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+udiv z0.b, p7/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udiv z0.b, p7/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udiv z0.h, p7/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udiv z0.h, p7/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+udiv z0.s, p7/m, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: udiv z0.s, p7/m, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+udiv z0.s, p8/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: udiv z0.s, p8/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/udiv.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/udiv.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/udiv.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/udiv.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+udiv z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: udiv z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x1f,0x95,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f 95 04 <unknown>
+
+udiv z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f d5 04 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/udivr-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/udivr-diagnostics.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/udivr-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/udivr-diagnostics.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+udivr z0.b, p7/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udivr z0.b, p7/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udivr z0.h, p7/m, z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udivr z0.h, p7/m, z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+udivr z0.s, p7/m, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: udivr z0.s, p7/m, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+udivr z0.s, p8/m, z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: udivr z0.s, p8/m, z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/udivr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/udivr.s?rev=337369&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/udivr.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/udivr.s Wed Jul 18 02:17:29 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+udivr z0.s, p7/m, z0.s, z31.s
+// CHECK-INST: udivr z0.s, p7/m, z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x1f,0x97,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f 97 04 <unknown>
+
+udivr z0.d, p7/m, z0.d, z31.d
+// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 1f d7 04 <unknown>
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