[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.cpp:550
+
   if (!isUInt<12>(Offset + Size)) {
     SOffset = AMDGPU::NoRegister;
----------------
t-tye wrote:
> Should this be Offset + Size - EltSize? Note that the loop is 0 based and increments by EltSize.
Yes, and this needs a very specific test to stress it


Repository:
  rL LLVM

https://reviews.llvm.org/D49448