[llvm] r337345 - Add PowerPC e500(v2) core scheduler and directives.
Justin Hibbits via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 17 21:24:49 PDT 2018
Author: jhibbits
Date: Tue Jul 17 21:24:49 2018
New Revision: 337345
URL: http://llvm.org/viewvc/llvm-project?rev=337345&view=rev
Log:
Add PowerPC e500(v2) core scheduler and directives.
Differential Revision: https://reviews.llvm.org/D44828
Added:
llvm/trunk/lib/Target/PowerPC/PPCScheduleE500.td
- copied, changed from r337344, llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
Modified:
llvm/trunk/lib/Target/PowerPC/PPC.td
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
Modified: llvm/trunk/lib/Target/PowerPC/PPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.td?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPC.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPC.td Tue Jul 17 21:24:49 2018
@@ -35,6 +35,8 @@ def Directive970 : SubtargetFeature<"",
def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
+def DirectiveE500 : SubtargetFeature<"", "DarwinDirective",
+ "PPC::DIR_E500", "">;
def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
"PPC::DIR_E500mc", "">;
def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
@@ -358,6 +360,10 @@ def : ProcessorModel<"g5", G5Model,
FeatureFRES, FeatureFRSQRTE,
Feature64Bit /*, Feature64BitRegs */,
FeatureMFTB, DeprecatedDST]>;
+def : ProcessorModel<"e500", PPCE500Model,
+ [DirectiveE500,
+ FeatureICBT, FeatureBookE,
+ FeatureISEL, FeatureMFTB]>;
def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE,
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Jul 17 21:24:49 2018
@@ -1486,6 +1486,7 @@ void PPCDarwinAsmPrinter::EmitStartOfAsm
"ppc750",
"ppc970",
"ppcA2",
+ "ppce500",
"ppce500mc",
"ppce5500",
"power3",
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jul 17 21:24:49 2018
@@ -1104,6 +1104,7 @@ PPCTargetLowering::PPCTargetLowering(con
default: break;
case PPC::DIR_970:
case PPC::DIR_A2:
+ case PPC::DIR_E500:
case PPC::DIR_E500mc:
case PPC::DIR_E5500:
case PPC::DIR_PWR4:
@@ -10822,6 +10823,7 @@ unsigned PPCTargetLowering::combineRepea
return 3;
case PPC::DIR_440:
case PPC::DIR_A2:
+ case PPC::DIR_E500:
case PPC::DIR_E500mc:
case PPC::DIR_E5500:
return 2;
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule.td?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule.td Tue Jul 17 21:24:49 2018
@@ -133,5 +133,6 @@ include "PPCScheduleP7.td"
include "PPCScheduleP8.td"
include "PPCScheduleP9.td"
include "PPCScheduleA2.td"
+include "PPCScheduleE500.td"
include "PPCScheduleE500mc.td"
include "PPCScheduleE5500.td"
Copied: llvm/trunk/lib/Target/PowerPC/PPCScheduleE500.td (from r337344, llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE500.td?p2=llvm/trunk/lib/Target/PowerPC/PPCScheduleE500.td&p1=llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td&r1=337344&r2=337345&rev=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE500.td Tue Jul 17 21:24:49 2018
@@ -1,4 +1,4 @@
-//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
+//===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,105 +7,92 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines the itinerary class data for the Freescale e500mc 32-bit
+// This file defines the itinerary class data for the Freescale e500 32-bit
// Power processor.
//
-// All information is derived from the "e500mc Core Reference Manual",
+// All information is derived from the "e500 Core Reference Manual",
// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
//
//===----------------------------------------------------------------------===//
-// Relevant functional units in the Freescale e500mc core:
+// Relevant functional units in the Freescale e500 core:
//
// * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
-// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
+// queues (GIQx) or Branch issue queue (BIQ).
def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute
-// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
-// Some instructions can only execute in SFX0 but not SFX1.
-// The CFX has a bypass path, allowing non-divide instructions to execute
-// while a divide instruction is executed.
-def E500_SFX0 : FuncUnit; // Simple unit 0
-def E500_SFX1 : FuncUnit; // Simple unit 1
+// 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
+// Some instructions can only execute in SU0 but not SU1.
+def E500_SU0 : FuncUnit; // Simple unit 0
+def E500_SU1 : FuncUnit; // Simple unit 1
def E500_BU : FuncUnit; // Branch unit
-def E500_CFX_DivBypass
- : FuncUnit; // CFX divide bypass path
-def E500_CFX_0 : FuncUnit; // CFX pipeline
+def E500_MU : FuncUnit; // MU pipeline
def E500_LSU_0 : FuncUnit; // LSU pipeline
-def E500_FPU_0 : FuncUnit; // FPU pipeline
def E500_GPR_Bypass : Bypass;
-def E500_FPR_Bypass : Bypass;
def E500_CR_Bypass : Bypass;
+def E500_DivBypass : Bypass;
-def PPCE500mcItineraries : ProcessorItineraries<
- [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
- E500_CFX_0, E500_LSU_0, E500_FPU_0],
- [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
+def PPCE500Itineraries : ProcessorItineraries<
+ [E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
+ E500_MU, E500_LSU_0],
+ [E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass,
E500_CR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[5, 1, 1], // Latency = 1 or 2
[E500_CR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0], 0>,
- InstrStage<14, [E500_CFX_DivBypass]>],
+ InstrStage<1, [E500_MU], 0>,
+ InstrStage<14, [E500_MU]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<8, [E500_FPU_0]>],
- [11], // Latency = 8
- [E500_FPR_Bypass]>,
- InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<8, [E500_FPU_0]>],
- [11, 1, 1], // Latency = 8
- [NoBypass, NoBypass, NoBypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_SFX0]>],
+ InstrStage<2, [E500_SU0]>],
[5, 1], // Latency = 2, Repeat rate = 2
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
@@ -122,7 +109,7 @@ def PPCE500mcItineraries : ProcessorItin
[4, 1], // Latency = 1
[E500_CR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
@@ -142,13 +129,13 @@ def PPCE500mcItineraries : ProcessorItin
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass],
@@ -158,7 +145,7 @@ def PPCE500mcItineraries : ProcessorItin
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass],
@@ -167,48 +154,17 @@ def PPCE500mcItineraries : ProcessorItin
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1, 1], // Latency = 3
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1, 1], // Latency = 3
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
- 2>, // 2 micro-ops
- InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
- 2>, // 2 micro-ops
- InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
- 2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
+ InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>,
@@ -228,96 +184,77 @@ def PPCE500mcItineraries : ProcessorItin
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ InstrStage<4, [E500_SU0]>],
[7, 1],
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_SFX0, E500_SFX1]>],
+ InstrStage<2, [E500_SU0, E500_SU1]>],
[5, 1], // Latency = 2, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ InstrStage<1, [E500_SU0]>],
[5, 1],
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0], 0>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<5, [E500_SFX0]>],
+ InstrStage<5, [E500_SU0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<5, [E500_SFX0]>],
+ InstrStage<5, [E500_SU0]>],
[8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ InstrStage<1, [E500_SU0]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ InstrStage<1, [E500_SU0]>],
[4, 1],
[NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_FPU_0]>],
- [11, 1, 1], // Latency = 8, Repeat rate = 2
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_FPU_0]>],
- [13, 1, 1], // Latency = 10, Repeat rate = 4
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_FPU_0]>],
- [11, 1, 1], // Latency = 8, Repeat rate = 2
- [E500_CR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<68, [E500_FPU_0]>],
- [71, 1, 1], // Latency = 68, Repeat rate = 68
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
+ InstrStage<32, [E500_MU]>],
+ [35, 1, 1], // Latency = 32, Repeat rate = 32
+ [E500_DivBypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<38, [E500_FPU_0]>],
- [41, 1, 1], // Latency = 38, Repeat rate = 38
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_FPU_0]>],
- [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass,
- E500_FPR_Bypass]>,
- InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<38, [E500_FPU_0]>],
- [41, 1], // Latency = 38, Repeat rate = 38
- [E500_FPR_Bypass, E500_FPR_Bypass]>
+ InstrStage<29, [E500_MU]>],
+ [32, 1, 1], // Latency = 29, Repeat rate = 29
+ [E500_DivBypass]>,
+ InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<1, [E500_SU0]>],
+ [4, 1, 1], // Latency = 1, Repeat rate = 1
+ [NoBypass]>,
+ InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
+ InstrStage<4, [E500_MU]>],
+ [7, 1, 1], // Latency = 4, Repeat rate = 1
+ [NoBypass]>
]>;
// ===---------------------------------------------------------------------===//
-// e500mc machine model for scheduling and other instruction cost heuristics.
+// e500 machine model for scheduling and other instruction cost heuristics.
-def PPCE500mcModel : SchedMachineModel {
+def PPCE500Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
@@ -325,5 +262,5 @@ def PPCE500mcModel : SchedMachineModel {
let CompleteModel = 0;
- let Itineraries = PPCE500mcItineraries;
+ let Itineraries = PPCE500Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td Tue Jul 17 21:24:49 2018
@@ -19,299 +19,299 @@
// * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
-def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
-def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
+def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 1
+def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute
// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
// Some instructions can only execute in SFX0 but not SFX1.
// The CFX has a bypass path, allowing non-divide instructions to execute
// while a divide instruction is executed.
-def E500_SFX0 : FuncUnit; // Simple unit 0
-def E500_SFX1 : FuncUnit; // Simple unit 1
-def E500_BU : FuncUnit; // Branch unit
-def E500_CFX_DivBypass
+def E500mc_SFX0 : FuncUnit; // Simple unit 0
+def E500mc_SFX1 : FuncUnit; // Simple unit 1
+def E500mc_BU : FuncUnit; // Branch unit
+def E500mc_CFX_DivBypass
: FuncUnit; // CFX divide bypass path
-def E500_CFX_0 : FuncUnit; // CFX pipeline
-def E500_LSU_0 : FuncUnit; // LSU pipeline
-def E500_FPU_0 : FuncUnit; // FPU pipeline
+def E500mc_CFX_0 : FuncUnit; // CFX pipeline
+def E500mc_LSU_0 : FuncUnit; // LSU pipeline
+def E500mc_FPU_0 : FuncUnit; // FPU pipeline
-def E500_GPR_Bypass : Bypass;
-def E500_FPR_Bypass : Bypass;
-def E500_CR_Bypass : Bypass;
+def E500mc_GPR_Bypass : Bypass;
+def E500mc_FPR_Bypass : Bypass;
+def E500mc_CR_Bypass : Bypass;
def PPCE500mcItineraries : ProcessorItineraries<
- [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
- E500_CFX_0, E500_LSU_0, E500_FPU_0],
- [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
- InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_DIS0, E500mc_DIS1, E500mc_SFX0, E500mc_SFX1, E500mc_BU, E500mc_CFX_DivBypass,
+ E500mc_CFX_0, E500mc_LSU_0, E500mc_FPU_0],
+ [E500mc_CR_Bypass, E500mc_GPR_Bypass, E500mc_FPR_Bypass], [
+ InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1, 1], // Latency = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass,
- E500_CR_Bypass]>,
- InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass,
+ E500mc_CR_Bypass]>,
+ InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[5, 1, 1], // Latency = 1 or 2
- [E500_CR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0], 0>,
- InstrStage<14, [E500_CFX_DivBypass]>],
+ [E500mc_CR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_CFX_0], 0>,
+ InstrStage<14, [E500mc_CFX_DivBypass]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<8, [E500_FPU_0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<8, [E500mc_FPU_0]>],
[11], // Latency = 8
- [E500_FPR_Bypass]>,
- InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<8, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<8, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8
[NoBypass, NoBypass, NoBypass]>,
- InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_CFX_0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_SFX0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<2, [E500mc_SFX0]>],
[5, 1], // Latency = 2, Repeat rate = 2
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_BU]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_BU]>],
[4, 1], // Latency = 1
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_BU]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_BU]>],
[4, 1, 1], // Latency = 1
- [E500_CR_Bypass,
- E500_CR_Bypass, E500_CR_Bypass]>,
- InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_BU]>],
+ [E500mc_CR_Bypass,
+ E500mc_CR_Bypass, E500mc_CR_Bypass]>,
+ InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_BU]>],
[4, 1], // Latency = 1
- [E500_CR_Bypass, E500_CR_Bypass]>,
- InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_CR_Bypass, E500mc_CR_Bypass]>,
+ InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
- [E500_CR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [NoBypass, E500_GPR_Bypass],
+ [NoBypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
+ [E500mc_FPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4
- [E500_FPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass],
+ [E500mc_FPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops
- InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
[7, 1], // Latency = r+3
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<3, [E500_LSU_0]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<3, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3
- [E500_GPR_Bypass,
- E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>]>,
- InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ [E500mc_GPR_Bypass,
+ E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>],
+ [6, 1], // Latency = 3
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0]>]>,
+ InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_SFX0]>],
[7, 1],
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<2, [E500mc_SFX0, E500mc_SFX1]>],
[5, 1], // Latency = 2, Repeat rate = 4
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0]>],
[5, 1],
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0], 0>]>,
- InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<5, [E500_SFX0]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_LSU_0], 0>]>,
+ InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<5, [E500mc_SFX0]>],
[8, 1],
- [E500_GPR_Bypass, E500_CR_Bypass]>,
- InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<5, [E500_SFX0]>],
+ [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
+ InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<5, [E500mc_SFX0]>],
[8, 1],
- [E500_GPR_Bypass, E500_CR_Bypass]>,
- InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
+ InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
- [E500_GPR_Bypass, E500_CR_Bypass]>,
- InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
+ InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0]>],
[4, 1], // Latency = 1, Repeat rate = 1
- [E500_CR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_SFX0]>],
+ [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0, E500_SFX1]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1
- [E500_CR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_SFX0]>],
+ [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<1, [E500mc_SFX0]>],
[4, 1],
- [NoBypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_FPU_0]>],
+ [NoBypass, E500mc_GPR_Bypass]>,
+ InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<2, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_FPU_0]>],
[13, 1, 1], // Latency = 10, Repeat rate = 4
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<2, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<2, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
- [E500_CR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<68, [E500_FPU_0]>],
+ [E500mc_CR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<68, [E500mc_FPU_0]>],
[71, 1, 1], // Latency = 68, Repeat rate = 68
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<38, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<38, [E500mc_FPU_0]>],
[41, 1, 1], // Latency = 38, Repeat rate = 38
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass]>,
- InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<4, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<4, [E500mc_FPU_0]>],
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4
- [E500_FPR_Bypass,
- E500_FPR_Bypass, E500_FPR_Bypass,
- E500_FPR_Bypass]>,
- InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<38, [E500_FPU_0]>],
+ [E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass, E500mc_FPR_Bypass,
+ E500mc_FPR_Bypass]>,
+ InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
+ InstrStage<38, [E500mc_FPU_0]>],
[41, 1], // Latency = 38, Repeat rate = 38
- [E500_FPR_Bypass, E500_FPR_Bypass]>
+ [E500mc_FPR_Bypass, E500mc_FPR_Bypass]>
]>;
// ===---------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=337345&r1=337344&r2=337345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Tue Jul 17 21:24:49 2018
@@ -46,6 +46,7 @@ namespace PPC {
DIR_750,
DIR_970,
DIR_A2,
+ DIR_E500,
DIR_E500mc,
DIR_E5500,
DIR_PWR3,
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