[llvm] r337334 - [X86] Remove the vector alignment requirement from the patterns added in r337320.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Jul 17 16:26:20 2018
New Revision: 337334

URL: http://llvm.org/viewvc/llvm-project?rev=337334&view=rev
Log:
[X86] Remove the vector alignment requirement from the patterns added in r337320.

The resulting instruction will only load 64 bits so alignment isn't required.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/vector-shuffle-sse1.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=337334&r1=337333&r2=337334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 17 16:26:20 2018
@@ -725,7 +725,8 @@ let Predicates = [UseSSE1] in {
 
   // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
   // end up with a movsd or bleand instead of shufp.
-  def : Pat<(X86Shufp (memopv4f32 addr:$src2), VR128:$src1, (i8 -28)),
+  // No need for aligned load, we're only loading 64-bits.
+  def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
             (MOVLPSrm VR128:$src1, addr:$src2)>;
 }
 
@@ -801,7 +802,8 @@ let Predicates = [UseSSE1] in {
 
   // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
   // end up with a movsd or bleand instead of shufp.
-  def : Pat<(X86Movlhps VR128:$src1, (memopv4f32 addr:$src2)),
+  // No need for aligned load, we're only loading 64-bits.
+  def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
             (MOVHPSrm VR128:$src1, addr:$src2)>;
 }
 

Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-sse1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-sse1.ll?rev=337334&r1=337333&r2=337334&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-sse1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-sse1.ll Tue Jul 17 16:26:20 2018
@@ -280,7 +280,7 @@ define <4 x float> @shuffle_mem_v4f32_01
 ; SSE1:       # %bb.0:
 ; SSE1-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; SSE1-NEXT:    retq
-  %b = load <4 x float>, <4 x float>* %pb, align 16
+  %b = load <4 x float>, <4 x float>* %pb, align 1
   %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x float> %shuffle
 }
@@ -300,7 +300,7 @@ define <4 x float> @shuffle_mem_v4f32_45
 ; SSE1:       # %bb.0:
 ; SSE1-NEXT:    movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
 ; SSE1-NEXT:    retq
-  %b = load <4 x float>, <4 x float>* %pb, align 16
+  %b = load <4 x float>, <4 x float>* %pb, align 1
   %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
   ret <4 x float> %shuffle
 }