[llvm] r337251 - [AArch64][SVE] Asm: Support for EXT instruction.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 17 01:39:48 PDT 2018
Author: s.desmalen
Date: Tue Jul 17 01:39:48 2018
New Revision: 337251
URL: http://llvm.org/viewvc/llvm-project?rev=337251&view=rev
Log:
[AArch64][SVE] Asm: Support for EXT instruction.
This patch adds an instruction that allows extracting
a vector from a pair of vectors, given an immediate index
that describes the element position to extract from.
The instruction has the following assembly:
ext z0.b, z0.b, z1.b, #imm
where #imm is an immediate between 0 and 255.
Added:
llvm/trunk/test/MC/AArch64/SVE/ext-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ext.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=337251&r1=337250&r2=337251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Tue Jul 17 01:39:48 2018
@@ -115,6 +115,7 @@ let Predicates = [HasSVE] in {
defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
defm INSR_ZR : sve_int_perm_insrs<"insr">;
defm INSR_ZV : sve_int_perm_insrv<"insr">;
+ def EXT_ZZI : sve_int_perm_extract_i<"ext">;
defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo">;
defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=337251&r1=337250&r2=337251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Tue Jul 17 01:39:48 2018
@@ -728,6 +728,26 @@ multiclass sve_int_perm_insrv<string asm
def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
}
+//===----------------------------------------------------------------------===//
+// SVE Permute - Extract Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_perm_extract_i<string asm>
+: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
+ asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
+ "", []>, Sched<[]> {
+ bits<5> Zdn;
+ bits<5> Zm;
+ bits<8> imm8;
+ let Inst{31-21} = 0b00000101001;
+ let Inst{20-16} = imm8{7-3};
+ let Inst{15-13} = 0b000;
+ let Inst{12-10} = imm8{2-0};
+ let Inst{9-5} = Zm;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+}
//===----------------------------------------------------------------------===//
// SVE Vector Select Group
Added: llvm/trunk/test/MC/AArch64/SVE/ext-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ext-diagnostics.s?rev=337251&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ext-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ext-diagnostics.s Tue Jul 17 01:39:48 2018
@@ -0,0 +1,33 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Tied operands must match
+
+ext z0.b, z1.b, z2.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: ext z0.b, z1.b, z2.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element widths.
+
+ext z0.h, z0.h, z1.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ext z0.h, z0.h, z1.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid immediate range.
+
+ext z0.b, z0.b, z1.b, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
+// CHECK-NEXT: ext z0.b, z0.b, z1.b, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ext z0.b, z0.b, z1.b, #256
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
+// CHECK-NEXT: ext z0.b, z0.b, z1.b, #256
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ext.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ext.s?rev=337251&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ext.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ext.s Tue Jul 17 01:39:48 2018
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ext z31.b, z31.b, z0.b, #0
+// CHECK-INST: ext z31.b, z31.b, z0.b, #0
+// CHECK-ENCODING: [0x1f,0x00,0x20,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 1f 00 20 05 <unknown>
+
+ext z31.b, z31.b, z0.b, #255
+// CHECK-INST: ext z31.b, z31.b, z0.b, #255
+// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>
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