[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In https://reviews.llvm.org/D49243#1163503, @avt77 wrote:

> Hi All,
>  I need your help!
>
> After my changes in sched models I got the following:
>
> ..../llvm/test/CodeGen/X86/schedule-x86_64.ll:2765:17: error: HASWELL-NEXT: expected string not found in input
>  ; HASWELL-NEXT: btcw %si, (%rdx) # sched: [1:2.75]
>
>   ^
>
> <stdin>:391:2: note: scanning from here
>  btcw %si, (%rdx) # sched: [6:1.00]
>  ^
>
> The new latency (6) looks more realistic than the current version (1) (rr version has 1 and mr version has 6) but throughput is unclear in both versions. What should I do? If I keep my version there could be to many changes in the current tests. Is it OK?


http://www.agner.org/optimize/instruction_tables.pdf, page 202, "Intel Haswell", "List of instruction timings and μop breakdown" appears to list all the BT* as having latency of 1.


https://reviews.llvm.org/D49243