[PATCH] D48637: [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic

[Daniel Cederman via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL337163: [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic (authored by dcederman, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48637?vs=153052&id=155649#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48637

Files:
  llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
  llvm/trunk/test/CodeGen/SPARC/trap.ll


Index: llvm/trunk/test/CodeGen/SPARC/trap.ll
===================================================================
--- llvm/trunk/test/CodeGen/SPARC/trap.ll
+++ llvm/trunk/test/CodeGen/SPARC/trap.ll
@@ -9,3 +9,13 @@
 }
 
 declare void @llvm.trap()
+
+; CHECK-LABEL: testdebugtrap:
+; CHECK: ta 1 ! encoding: [0x91,0xd0,0x20,0x01]
+define void @testdebugtrap() {
+entry:
+  call void @llvm.debugtrap()
+  ret void
+}
+
+declare void @llvm.debugtrap()
Index: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1727,6 +1727,7 @@
   setOperationAction(ISD::VAARG             , MVT::Other, Custom);
 
   setOperationAction(ISD::TRAP              , MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP         , MVT::Other, Legal);
 
   // Use the default implementation.
   setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
Index: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
@@ -1009,6 +1009,9 @@
 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
   def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
 
+def : Pat<(debugtrap),
+  (TRAPri (i32 G0), (i32 1), (i32 8))>;
+
 // Section B.28 - Read State Register Instructions
 let rs2 = 0 in
   def RDASR : F3_1<2, 0b101000,


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