[PATCH] D49336: [x86/SLH] Teach speculative load hardening to correctly harden the indices used by AVX2 and AVX-512 gather instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:9591
                        RegisterClass KRC, X86MemOperand memop> {
-  let Predicates = [HasPFI], hasSideEffects = 1 in
+  let Predicates = [HasPFI], mayLoad = 1, hasSideEffects = 1 in
   def m  : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
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I wonder if this should be mayLoad=1, mayStore =1, hasSideEffects = 0. That's what we use for other prefetch instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D49336