[PATCH] D49196: [llvm-mca][BtVer2] teach how to identify false dependencies on partially written registers.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.

LGTM with a couple of final minor docs/comments fixes.



================
Comment at: include/llvm/Target/TargetSchedule.td:465-466
+//
+// This implementation assumes that there is no limit in the number of renames
+// per cycle. Also, there is no limit to how many times the same logical
+// register can be renamed during the same cycle.
----------------
lebedev.ri wrote:
> This should probably be a TODO.
> "Software Optimization Guide for AMD Family 17h Processors"
> http://developer.amd.com/wordpress/media/2013/12/55723_SOG_Fam_17h_Processors_3.00.pdf
> "34 Microarchitecture of AMD Family 17h Processor Chapter 2"
> "2.11 Floating-Point Unit"
>    It can handle dispatch and renaming of 4 floating point micro ops per cycle
> 
> So maybe having one single `DispatchWidth` per `ProcResGroup` and using that for
> both the dispatch and renaming is the way to go.
Yes, please put a TODO in front of this paragraph:
```
TODO: This implementation currently assumes that there is no limit in the number of renames per cycle, which might not be true for all hardware or register classes.
```


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:50
+// Reference: Section 18.13 "Partial register access" - Agner Fog's
+// "microarchitecture.pdf".
+def JIntegerPRF : RegisterFile<64, [GR64, CCR]>;
----------------
Please can you check the section numbers - it doesn't seem to match the latest version of Agner's doc - as he seems to reorder things with each release, adding the full secton/subsection titles might make sense here.


https://reviews.llvm.org/D49196