[PATCH] D49315: [X86][SLH] Remove PDEP and PEXT from isDataInvariantLoad

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: chandlerc.

Ryzen has something like an 18 cycle latency on these based on Agner's data. AMD's own xls is blank. So it seems like there might be something tricky here. Might be safer to remove them. We never generate them without an intrinsic so this might be ok.


https://reviews.llvm.org/D49315

Files:
  lib/Target/X86/X86SpeculativeLoadHardening.cpp


Index: lib/Target/X86/X86SpeculativeLoadHardening.cpp
===================================================================
--- lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -917,10 +917,6 @@
   case X86::MULX64rm:
 
     // Arithmetic instructions that are both constant time and don't set flags.
-  case X86::PDEP32rm:
-  case X86::PDEP64rm:
-  case X86::PEXT32rm:
-  case X86::PEXT64rm:
   case X86::RORX32mi:
   case X86::RORX64mi:
   case X86::SARX32rm:


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