[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/Target/X86/X86Schedule.td:122
+// Bit Test
+defm WriteBTr    : X86SchedWritePair;
+
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RKSimon wrote:
> lebedev.ri wrote:
> > Hmm. Nits:
> > 1. (not a nit) The suffix `r` notes that only the non-mem versions are covered.
> >    I wonder if we can convey that somehow better.
> > 2. These cover 4 different bit-test instructions - `bt`,`bt[rcs]`
> >    Naming this `WriteBTr` //may// be confizing - is this only about `bt` instruction?
> >    How about calling it `WriteBitTest`?
> I'm confused - this should be probably be called WriteBT. But then you've declared this as a X86SchedWritePair but you're not using the folded half of the pair?
Note that it *only* covers `rr` versions, and does not include `mr` versions.
So yeah, maybe it shouldn't be `X86SchedWritePair`, but `X86WriteRes`?


https://reviews.llvm.org/D49243