[PATCH] D49290: [Mips][FastISel] Fix handling of icmp with i1 type.

[Dragan Mladjenovic via Phabricator via llvm-commits]

draganm created this revision.
draganm added a reviewer: atanasyan.
Herald added subscribers: arichardson, sdardis.

The Mips FastISel back-end does not extend i1 values while lowering icmp.  Ensure that we bail into DAG ISel when handling this case.


https://reviews.llvm.org/D49290

Files:
  lib/Target/Mips/MipsFastISel.cpp
  test/CodeGen/Mips/Fast-ISel/icmpi1.ll


Index: test/CodeGen/Mips/Fast-ISel/icmpi1.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/Fast-ISel/icmpi1.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN:     < %s -verify-machineinstrs | FileCheck %s
+
+
+define zeroext i1 @foo(i8* nocapture readonly) {
+; CHECK-LABEL: foo
+; CHECK:         lbu $[[REG0:[0-9]+]], 0($4)
+; CHECK-NEXT:    xori $[[REG1:[0-9]+]], $[[REG0]], 1
+; CHECK-NEXT:    andi $2, $[[REG1]], 1
+  %2 = load i8, i8* %0, align 1
+  %3 = trunc i8 %2 to i1
+  %4 = icmp ne i1 %3, true
+  ret i1 %4
+}
Index: lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- lib/Target/Mips/MipsFastISel.cpp
+++ lib/Target/Mips/MipsFastISel.cpp
@@ -2062,6 +2062,10 @@
   if (VReg == 0)
     return 0;
   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
+
+  if (VMVT == MVT::i1)
+    return 0;
+
   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))


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