[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added a comment.

In https://reviews.llvm.org/D49243#1160224, @lebedev.ri wrote:

> I'm assuming that you have run `ninja check-llvm-tools-llvm-mca-x86` and it was ok. (the test coverage seems to be ok as-is.)


Usually I'm using "check-all" but I'll try "check-llvm-tools-llvm-mca-x86" as well. Yes, it works.



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Comment at: lib/Target/X86/X86InstrInfo.td:1799
 // other operand is in a register. When it's an immediate, bt is still fast.
 let SchedRW = [WriteALU] in {
 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
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RKSimon wrote:
> Why isn't this WriteBTLd ?
This patch does not deal with mem at all but I'm going to do it asap.


https://reviews.llvm.org/D49243