[llvm] r336913 - [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions

[Ahmed Bougacha via llvm-commits]

Hey Sjoerd,

On Thu, Jul 12, 2018 at 7:57 AM, Sjoerd Meijer via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: sjoerdmeijer
> Date: Thu Jul 12 07:57:59 2018
> New Revision: 336913
>
> URL: http://llvm.org/viewvc/llvm-project?rev=336913&view=rev
> Log:
> [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions
>
> These instructions are added to AArch64 only.
>
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>     llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>     llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=336913&r1=336912&r2=336913&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Thu Jul 12 07:57:59 2018
> @@ -3405,6 +3405,19 @@ class BaseLoadStoreUnscale<bits<2> sz, b
>    let DecoderMethod = "DecodeSignedLdStInstruction";
>  }
>
> +// Armv8.4 LDAPR & STLR with Immediate Offset instruction
> +multiclass BaseLoadStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
> +                                   RegisterOperand regtype > {
> +  def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
> +                               (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
> +          Sched<[WriteST]> {
> +    let Inst{29} = 0;
> +    let Inst{24} = 1;
> +  }
> +  def : InstAlias<asm # "\t$Rt, [$Rn]",
> +                  (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
> +}
> +
>  multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
>                     string asm, list<dag> pattern> {
>    let AddedComplexity = 1 in // try this before LoadUI
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=336913&r1=336912&r2=336913&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Jul 12 07:57:59 2018
> @@ -2430,6 +2430,23 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b0
>                           [(truncstorei8 GPR32z:$Rt,
>                                    (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
>
> +// Armv8.4 LDAPR & STLR with Immediate Offset instruction
> +let Predicates = [HasV8_4a] in {
> +defm STLURB     : BaseLoadStoreUnscaleV84<"stlurb",   0b00, 0b00, GPR32>;
> +defm STLURH     : BaseLoadStoreUnscaleV84<"stlurh",   0b01, 0b00, GPR32>;
> +defm STLUR      : BaseLoadStoreUnscaleV84<"stlur",    0b10, 0b00, GPR32>;
> +defm STLUR64    : BaseLoadStoreUnscaleV84<"stlur",    0b11, 0b00, GPR64>;

Not a big deal, but the usual convention elsewhere in the file would
be to call these "STLURWi" and "STLURXi", no?

> +defm LDAPURB    : BaseLoadStoreUnscaleV84<"ldapurb",  0b00, 0b01, GPR32>;
> +defm LDAPURSB   : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
> +defm LDAPURSB64 : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;

and these "LDAPURSBWi" and "LDAPURSBXi", I guess ;)

-Ahmed

> +defm LDAPURH    : BaseLoadStoreUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;
> +defm LDAPURSH   : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
> +defm LDAPURSH64 : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
> +defm LDAPUR     : BaseLoadStoreUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
> +defm LDAPURSW   : BaseLoadStoreUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
> +defm LDAPUR64   : BaseLoadStoreUnscaleV84<"ldapur",   0b11, 0b01, GPR64>;
> +}
> +
>  // Match all store 64 bits width whose type is compatible with FPR64
>  def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
>            (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
>
> Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=336913&r1=336912&r2=336913&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Thu Jul 12 07:57:59 2018
> @@ -1183,6 +1183,14 @@ static DecodeStatus DecodeSignedLdStInst
>    case AArch64::LDRHHpost:
>    case AArch64::STRWpost:
>    case AArch64::LDRWpost:
> +  case AArch64::STLURBi:
> +  case AArch64::STLURHi:
> +  case AArch64::STLURi:
> +  case AArch64::LDAPURBi:
> +  case AArch64::LDAPURSBi:
> +  case AArch64::LDAPURHi:
> +  case AArch64::LDAPURSHi:
> +  case AArch64::LDAPURi:
>      DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
>      break;
>    case AArch64::LDURSBXi:
> @@ -1205,6 +1213,11 @@ static DecodeStatus DecodeSignedLdStInst
>    case AArch64::STRXpost:
>    case AArch64::LDRSWpost:
>    case AArch64::LDRXpost:
> +  case AArch64::LDAPURSWi:
> +  case AArch64::LDAPURSH64i:
> +  case AArch64::LDAPURSB64i:
> +  case AArch64::STLUR64i:
> +  case AArch64::LDAPUR64i:
>      DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
>      break;
>    case AArch64::LDURQi:
>
>
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