[llvm] r336940 - [PowerPC] [NFC] Update __float128 tests
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 12 13:18:57 PDT 2018
Author: stefanp
Date: Thu Jul 12 13:18:57 2018
New Revision: 336940
URL: http://llvm.org/viewvc/llvm-project?rev=336940&view=rev
Log:
[PowerPC] [NFC] Update __float128 tests
Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to
the __float128 tests. Then modify the tests as required.
Modified:
llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll
llvm/trunk/test/CodeGen/PowerPC/f128-compare.ll
llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
llvm/trunk/test/CodeGen/PowerPC/f128-fma.ll
llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll
llvm/trunk/test/CodeGen/PowerPC/f128-rounding.ll
llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll Thu Jul 12 13:18:57 2018
@@ -1,7 +1,9 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s \
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck -check-prefix=CHECK-BE %s
; Testing homogeneous aggregates.
@@ -15,11 +17,11 @@
define fp128 @testArray_01(fp128* nocapture readonly %sa) {
; CHECK-LABEL: testArray_01:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 34, 32(3)
+; CHECK-NEXT: lxv v2, 32(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testArray_01:
-; CHECK-BE: lxv 34, 32(3)
+; CHECK-BE: lxv v2, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2
@@ -31,13 +33,13 @@ entry:
define fp128 @testArray_02() {
; CHECK-LABEL: testArray_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
-; CHECK-NEXT: lxv 34, 32(3)
+; CHECK-NEXT: addis r3, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r3, .LC0 at toc@l(r3)
+; CHECK-NEXT: lxv v2, 32(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testArray_02:
-; CHECK-BE: lxv 34, 32(3)
+; CHECK-BE: lxv v2, 32(r3)
; CHECK-BE-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1,
@@ -62,11 +64,11 @@ entry:
define fp128 @testStruct_02([8 x fp128] %a.coerce) {
; CHECK-LABEL: testStruct_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr 2, 9
+; CHECK-NEXT: vmr v2, v9
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_02:
-; CHECK-BE: vmr 2, 9
+; CHECK-BE: vmr v2, v9
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7
@@ -80,28 +82,28 @@ define fp128 @testStruct_03(%struct.With
align 16 %a) {
; CHECK-LABEL: testStruct_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 34, 128(1)
-; CHECK-NEXT: std 10, 88(1)
-; CHECK-NEXT: std 9, 80(1)
-; CHECK-NEXT: std 8, 72(1)
-; CHECK-NEXT: std 7, 64(1)
-; CHECK-NEXT: std 6, 56(1)
-; CHECK-NEXT: std 5, 48(1)
-; CHECK-NEXT: std 4, 40(1)
-; CHECK-NEXT: std 3, 32(1)
+; CHECK-NEXT: lxv v2, 128(r1)
+; CHECK-NEXT: std r10, 88(r1)
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: std r3, 32(r1)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_03:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: lxv 34, 144(1)
-; CHECK-BE-NEXT: std 10, 104(1)
-; CHECK-BE-NEXT: std 9, 96(1)
-; CHECK-BE-NEXT: std 8, 88(1)
-; CHECK-BE-NEXT: std 7, 80(1)
-; CHECK-BE-NEXT: std 6, 72(1)
-; CHECK-BE-NEXT: std 5, 64(1)
-; CHECK-BE-NEXT: std 4, 56(1)
-; CHECK-BE-NEXT: std 3, 48(1)
+; CHECK-BE-NEXT: lxv v2, 144(r1)
+; CHECK-BE-NEXT: std r10, 104(r1)
+; CHECK-BE-NEXT: std r9, 96(r1)
+; CHECK-BE-NEXT: std r8, 88(r1)
+; CHECK-BE-NEXT: std r7, 80(r1)
+; CHECK-BE-NEXT: std r6, 72(r1)
+; CHECK-BE-NEXT: std r5, 64(r1)
+; CHECK-BE-NEXT: std r4, 56(r1)
+; CHECK-BE-NEXT: std r3, 48(r1)
; CHECK-BE-NEXT: blr
entry:
%a7 = getelementptr inbounds %struct.With9fp128params,
@@ -114,11 +116,11 @@ entry:
define fp128 @testStruct_04([8 x fp128] %a.coerce) {
; CHECK-LABEL: testStruct_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr 2, 5
+; CHECK-NEXT: vmr v2, v5
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_04:
-; CHECK-BE: vmr 2, 5
+; CHECK-BE: vmr v2, v5
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3
@@ -157,12 +159,12 @@ entry:
define fp128 @testHUnion_03([3 x fp128] %a.coerce) {
; CHECK-LABEL: testHUnion_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testHUnion_03:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr 2, 3
+; CHECK-BE-NEXT: vmr v2, v3
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1
@@ -173,12 +175,12 @@ entry:
define fp128 @testHUnion_04([3 x fp128] %a.coerce) {
; CHECK-LABEL: testHUnion_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmr 2, 4
+; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testHUnion_04:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vmr 2, 4
+; CHECK-BE-NEXT: vmr v2, v4
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2
@@ -194,11 +196,11 @@ entry:
define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
; CHECK-LABEL: testMixedAggregate:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrdd 34, 8, 7
+; CHECK-NEXT: mtvsrdd v2, r8, r7
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testMixedAggregate:
-; CHECK-BE: mtvsrdd 34, 8, 7
+; CHECK-BE: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2
@@ -210,11 +212,11 @@ entry:
define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
; CHECK-LABEL: testMixedAggregate_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrdd 34, 6, 5
+; CHECK-NEXT: mtvsrdd v2, r6, r5
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testMixedAggregate_02:
-; CHECK-BE: mtvsrdd 34, 6, 5
+; CHECK-BE: mtvsrdd v2, r6, r5
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1
@@ -226,13 +228,13 @@ entry:
define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-LABEL: testMixedAggregate_03:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: mtvsrwa 34, 3
-; CHECK-DAG: mtvsrdd 35, 6, 5
-; CHECK: mtvsrd 36, 10
-; CHECK: xscvsdqp 2, 2
-; CHECK-DAG: xscvsdqp [[REG:[0-9]+]], 4
-; CHECK-DAG: xsaddqp 2, 3, 2
-; CHECK: xsaddqp 2, 2, [[REG]]
+; CHECK-DAG: mtvsrwa v2, r3
+; CHECK-DAG: mtvsrdd v3, r6, r5
+; CHECK: mtvsrd v4, r10
+; CHECK: xscvsdqp v2, v2
+; CHECK-DAG: xscvsdqp v[[REG:[0-9]+]], v4
+; CHECK-DAG: xsaddqp v2, v3, v2
+; CHECK: xsaddqp v2, v2, v[[REG]]
; CHECK-NEXT: blr
entry:
%sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0
@@ -254,28 +256,28 @@ entry:
define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
; CHECK-LABEL: testNestedAggregate:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: std 8, 72(1)
-; CHECK-NEXT: std 7, 64(1)
-; CHECK-NEXT: std 10, 88(1)
-; CHECK-NEXT: std 9, 80(1)
-; CHECK-NEXT: lxv 34, 64(1)
-; CHECK-NEXT: std 6, 56(1)
-; CHECK-NEXT: std 5, 48(1)
-; CHECK-NEXT: std 4, 40(1)
-; CHECK-NEXT: std 3, 32(1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: std r10, 88(r1)
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: lxv v2, 64(r1)
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: std r3, 32(r1)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testNestedAggregate:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: std 8, 88(1)
-; CHECK-BE-NEXT: std 7, 80(1)
-; CHECK-BE-NEXT: std 10, 104(1)
-; CHECK-BE-NEXT: std 9, 96(1)
-; CHECK-BE-NEXT: lxv 34, 80(1)
-; CHECK-BE-NEXT: std 6, 72(1)
-; CHECK-BE-NEXT: std 5, 64(1)
-; CHECK-BE-NEXT: std 4, 56(1)
-; CHECK-BE-NEXT: std 3, 48(1)
+; CHECK-BE-NEXT: std r8, 88(r1)
+; CHECK-BE-NEXT: std r7, 80(r1)
+; CHECK-BE-NEXT: std r10, 104(r1)
+; CHECK-BE-NEXT: std r9, 96(r1)
+; CHECK-BE-NEXT: lxv v2, 80(r1)
+; CHECK-BE-NEXT: std r6, 72(r1)
+; CHECK-BE-NEXT: std r5, 64(r1)
+; CHECK-BE-NEXT: std r4, 56(r1)
+; CHECK-BE-NEXT: std r3, 48(r1)
; CHECK-BE-NEXT: blr
entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
@@ -287,11 +289,11 @@ entry:
define fp128 @testUnion_01([1 x i128] %a.coerce) {
; CHECK-LABEL: testUnion_01:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrdd 34, 4, 3
+; CHECK-NEXT: mtvsrdd v2, r4, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testUnion_01:
-; CHECK-BE: mtvsrdd 34, 4, 3
+; CHECK-BE: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
@@ -303,11 +305,11 @@ entry:
define fp128 @testUnion_02([1 x i128] %a.coerce) {
; CHECK-LABEL: testUnion_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrdd 34, 4, 3
+; CHECK-NEXT: mtvsrdd v2, r4, r3
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testUnion_02:
-; CHECK-BE: mtvsrdd 34, 4, 3
+; CHECK-BE: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0
@@ -319,11 +321,11 @@ entry:
define fp128 @testUnion_03([4 x i128] %a.coerce) {
; CHECK-LABEL: testUnion_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrdd 34, 8, 7
+; CHECK-NEXT: mtvsrdd v2, r8, r7
; CHECK-NEXT: blr
; CHECK-BE-LABEL: testUnion_03:
-; CHECK-BE: mtvsrdd 34, 8, 7
+; CHECK-BE: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: blr
entry:
%a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2
@@ -335,26 +337,26 @@ entry:
define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 11, 2, .LCPI17_0 at toc@ha
-; CHECK-NEXT: cmpwi 0, 3, 1
-; CHECK-NEXT: std 10, 88(1)
-; CHECK-NEXT: std 9, 80(1)
-; CHECK-NEXT: std 8, 72(1)
-; CHECK-NEXT: std 7, 64(1)
-; CHECK-NEXT: std 6, 56(1)
-; CHECK-NEXT: std 5, 48(1)
-; CHECK-NEXT: std 4, 40(1)
-; CHECK-NEXT: addi 11, 11, .LCPI17_0 at toc@l
-; CHECK-NEXT: lxvx 34, 0, 11
-; CHECK-NEXT: bltlr 0
+; CHECK-NEXT: addis r11, r2, .LCPI17_0 at toc@ha
+; CHECK-NEXT: cmpwi cr0, r3, 1
+; CHECK-NEXT: std r10, 88(r1)
+; CHECK-NEXT: std r9, 80(r1)
+; CHECK-NEXT: std r8, 72(r1)
+; CHECK-NEXT: std r7, 64(r1)
+; CHECK-NEXT: std r6, 56(r1)
+; CHECK-NEXT: std r5, 48(r1)
+; CHECK-NEXT: std r4, 40(r1)
+; CHECK-NEXT: addi r11, r11, .LCPI17_0 at toc@l
+; CHECK-NEXT: lxvx v2, 0, r11
+; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end
-; CHECK-NEXT: addi 3, 1, 40
-; CHECK-NEXT: lxvx 35, 0, 3
-; CHECK-NEXT: xsaddqp 2, 3, 2
-; CHECK-NEXT: lxv 35, 16(3)
-; CHECK-NEXT: addi 3, 1, 72
-; CHECK-NEXT: std 3, -8(1)
-; CHECK-NEXT: xsaddqp 2, 2, 3
+; CHECK-NEXT: addi r3, r1, 40
+; CHECK-NEXT: lxvx v3, 0, r3
+; CHECK-NEXT: xsaddqp v2, v3, v2
+; CHECK-NEXT: lxv v3, 16(r3)
+; CHECK-NEXT: addi r3, r1, 72
+; CHECK-NEXT: std r3, -8(r1)
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry:
%ap = alloca i8*, align 8
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll Thu Jul 12 13:18:57 2018
@@ -1,5 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function Attrs: norecurse nounwind
define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
@@ -151,7 +152,7 @@ entry:
define fp128 @qp_sin(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_sin:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl sinf128
; CHECK: blr
entry:
@@ -163,7 +164,7 @@ declare fp128 @llvm.sin.f128(fp128 %Val)
define fp128 @qp_cos(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_cos:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl cosf128
; CHECK: blr
entry:
@@ -175,7 +176,7 @@ declare fp128 @llvm.cos.f128(fp128 %Val)
define fp128 @qp_log(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_log:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl logf128
; CHECK: blr
entry:
@@ -187,7 +188,7 @@ declare fp128 @llvm.log.f128(fp128 %
define fp128 @qp_log10(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_log10:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl log10f128
; CHECK: blr
entry:
@@ -199,7 +200,7 @@ declare fp128 @llvm.log10.f128(fp128
define fp128 @qp_log2(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_log2:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl log2f128
; CHECK: blr
entry:
@@ -212,8 +213,8 @@ declare fp128 @llvm.log2.f128(fp128
define fp128 @qp_minnum(fp128* nocapture readonly %a,
fp128* nocapture readonly %b) {
; CHECK-LABEL: qp_minnum:
-; CHECK: lxv 34, 0(3)
-; CHECK: lxv 35, 0(4)
+; CHECK: lxv v2, 0(r3)
+; CHECK: lxv v3, 0(r4)
; CHECK: bl fminf128
; CHECK: blr
entry:
@@ -227,8 +228,8 @@ declare fp128 @llvm.minnum.f128(fp12
define fp128 @qp_maxnum(fp128* nocapture readonly %a,
fp128* nocapture readonly %b) {
; CHECK-LABEL: qp_maxnum:
-; CHECK: lxv 34, 0(3)
-; CHECK: lxv 35, 0(4)
+; CHECK: lxv v2, 0(r3)
+; CHECK: lxv v3, 0(r4)
; CHECK: bl fmaxf128
; CHECK: blr
entry:
@@ -242,8 +243,8 @@ declare fp128 @llvm.maxnum.f128(fp12
define fp128 @qp_pow(fp128* nocapture readonly %a,
fp128* nocapture readonly %b) {
; CHECK-LABEL: qp_pow:
-; CHECK: lxv 34, 0(3)
-; CHECK: lxv 35, 0(4)
+; CHECK: lxv v2, 0(r3)
+; CHECK: lxv v3, 0(r4)
; CHECK: bl powf128
; CHECK: blr
entry:
@@ -256,7 +257,7 @@ declare fp128 @llvm.pow.f128(fp128 %Val,
define fp128 @qp_exp(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_exp:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl expf128
; CHECK: blr
entry:
@@ -268,7 +269,7 @@ declare fp128 @llvm.exp.f128(fp128 %
define fp128 @qp_exp2(fp128* nocapture readonly %a) {
; CHECK-LABEL: qp_exp2:
-; CHECK: lxv 34, 0(3)
+; CHECK: lxv v2, 0(r3)
; CHECK: bl exp2f128
; CHECK: blr
entry:
@@ -281,8 +282,8 @@ declare fp128 @llvm.exp2.f128(fp128
define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,
fp128* nocapture %res) {
; CHECK-LABEL: qp_powi:
-; CHECK: lxv 34, 0(3)
-; CHECK: lwz 3, 0(4)
+; CHECK: lxv v2, 0(r3)
+; CHECK: lwz r3, 0(r4)
; CHECK: bl __powikf2
; CHECK: blr
entry:
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-compare.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-compare.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-compare.ll Thu Jul 12 13:18:57 2018
@@ -1,5 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
@b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
@@ -14,7 +15,7 @@ entry:
ret i32 %conv
; CHECK-LABEL: greater_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, gt
; CHECK: blr
}
@@ -28,7 +29,7 @@ entry:
ret i32 %conv
; CHECK-LABEL: less_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, lt
; CHECK: blr
}
@@ -42,8 +43,8 @@ entry:
ret i32 %conv
; CHECK-LABEL: greater_eq_qp
; CHECK: xscmpuqp
-; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 0
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK: cror 4*cr[[REG:[0-9]+]]+lt, un, lt
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
; CHECK: blr
}
@@ -57,8 +58,8 @@ entry:
ret i32 %conv
; CHECK-LABEL: less_eq_qp
; CHECK: xscmpuqp
-; CHECK: cror [[REG:[0-9]+]], {{[0-9]+}}, 1
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK: cror 4*cr[[REG:[0-9]+]]+lt, un, gt
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
; CHECK: blr
}
@@ -72,7 +73,7 @@ entry:
ret i32 %conv
; CHECK-LABEL: equal_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
+; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, eq
; CHECK: blr
}
@@ -87,7 +88,7 @@ entry:
ret i32 %lnot.ext
; CHECK-LABEL: not_greater_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, gt
; CHECK: blr
}
@@ -102,7 +103,7 @@ entry:
ret i32 %lnot.ext
; CHECK-LABEL: not_less_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, lt
; CHECK: blr
}
@@ -117,8 +118,8 @@ entry:
ret i32 %lnot.ext
; CHECK-LABEL: not_greater_eq_qp
; CHECK: xscmpuqp
-; CHECK: crnor [[REG:[0-9]+]], 0, {{[0-9]+}}
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, lt, un
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
; CHECK: blr
}
@@ -133,8 +134,8 @@ entry:
ret i32 %lnot.ext
; CHECK-LABEL: not_less_eq_qp
; CHECK: xscmpuqp
-; CHECK: crnor [[REG:[0-9]+]], 1, {{[0-9]+}}
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, gt, un
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
; CHECK: blr
}
@@ -148,7 +149,7 @@ entry:
ret i32 %conv
; CHECK-LABEL: not_equal_qp
; CHECK: xscmpuqp
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, 2
+; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, eq
; CHECK: blr
}
@@ -161,8 +162,8 @@ entry:
%cond = select i1 %cmp, fp128 %0, fp128 %1
ret fp128 %cond
; CHECK-LABEL: greater_sel_qp
-; CHECK: xscmpuqp [[REG:[0-9]+]]
-; CHECK: bgtlr [[REG]]
+; CHECK: xscmpuqp cr[[REG:[0-9]+]]
+; CHECK: bgtlr cr[[REG]]
; CHECK: blr
}
@@ -175,8 +176,8 @@ entry:
%cond = select i1 %cmp, fp128 %0, fp128 %1
ret fp128 %cond
; CHECK-LABEL: less_sel_qp
-; CHECK: xscmpuqp [[REG:[0-9]+]]
-; CHECK: bltlr [[REG]]
+; CHECK: xscmpuqp cr[[REG:[0-9]+]]
+; CHECK: bltlr cr[[REG]]
; CHECK: blr
}
@@ -190,8 +191,8 @@ entry:
ret fp128 %cond
; CHECK-LABEL: greater_eq_sel_qp
; CHECK: xscmpuqp
-; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 0
-; CHECK: bclr {{[0-9]+}}, [[REG]]
+; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, un, lt
+; CHECK: bclr {{[0-9]+}}, 4*cr[[REG]]+lt, 0
; CHECK: blr
}
@@ -205,8 +206,8 @@ entry:
ret fp128 %cond
; CHECK-LABEL: less_eq_sel_qp
; CHECK: xscmpuqp
-; CHECK: crnor [[REG:[0-9]+]], {{[0-9]+}}, 1
-; CHECK: bclr {{[0-9]+}}, [[REG]]
+; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, un, gt
+; CHECK: bclr {{[0-9]+}}, 4*cr[[REG]]+lt, 0
; CHECK: blr
}
@@ -219,7 +220,7 @@ entry:
%cond = select i1 %cmp, fp128 %0, fp128 %1
ret fp128 %cond
; CHECK-LABEL: equal_sel_qp
-; CHECK: xscmpuqp [[REG:[0-9]+]]
-; CHECK: beqlr [[REG]]
+; CHECK: xscmpuqp cr[[REG:[0-9]+]]
+; CHECK: beqlr cr[[REG]]
; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll Thu Jul 12 13:18:57 2018
@@ -1,6 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@@ -17,9 +17,9 @@ entry:
ret void
; CHECK-LABEL: sdwConv2qp
-; CHECK: mtvsrd [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrd v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -33,11 +33,11 @@ entry:
ret void
; CHECK-LABEL: sdwConv2qp_02
-; CHECK: addis [[REG:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK: ld [[REG]], .LC0 at toc@l([[REG]])
-; CHECK: lxsd [[REG0:[0-9]+]], 16([[REG]])
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK: ld r[[REG]], .LC0 at toc@l(r[[REG]])
+; CHECK: lxsd v[[REG0:[0-9]+]], 16(r[[REG]])
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -51,9 +51,9 @@ entry:
; CHECK-LABEL: sdwConv2qp_03
; CHECK-NOT: ld
-; CHECK: lxsd [[REG0:[0-9]+]], 0(4)
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsd v[[REG0:[0-9]+]], 0(r4)
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -65,9 +65,9 @@ entry:
ret void
; CHECK-LABEL: udwConv2qp
-; CHECK: mtvsrd [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrd v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -81,11 +81,11 @@ entry:
ret void
; CHECK-LABEL: udwConv2qp_02
-; CHECK: addis [[REG:[0-9]+]], 2, .LC1 at toc@ha
-; CHECK: ld [[REG]], .LC1 at toc@l([[REG]])
-; CHECK: lxsd [[REG0:[0-9]+]], 32([[REG]])
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC1 at toc@ha
+; CHECK: ld r[[REG]], .LC1 at toc@l(r[[REG]])
+; CHECK: lxsd v[[REG0:[0-9]+]], 32(r[[REG]])
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -99,9 +99,9 @@ entry:
; CHECK-LABEL: udwConv2qp_03
; CHECK-NOT: ld
-; CHECK: lxsd [[REG:[0-9]+]], 0(4)
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsd v[[REG:[0-9]+]], 0(r4)
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -117,9 +117,9 @@ entry:
ret fp128* %sink
; CHECK-LABEL: sdwConv2qp_testXForm
-; CHECK: lxsdx [[REG:[0-9]+]],
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsdx v[[REG:[0-9]+]],
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -135,9 +135,9 @@ entry:
ret fp128* %sink
; CHECK-LABEL: udwConv2qp_testXForm
-; CHECK: lxsdx [[REG:[0-9]+]],
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsdx v[[REG:[0-9]+]],
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -150,9 +150,9 @@ entry:
; CHECK-LABEL: swConv2qp
; CHECK-NOT: lwz
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -166,9 +166,9 @@ entry:
; CHECK-LABEL: swConv2qp_02
; CHECK-NOT: lwz
-; CHECK: lxsiwax [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsiwax v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -182,12 +182,12 @@ entry:
ret void
; CHECK-LABEL: swConv2qp_03
-; CHECK: addis [[REG:[0-9]+]], 2, .LC2 at toc@ha
-; CHECK: ld [[REG]], .LC2 at toc@l([[REG]])
-; CHECK: addi [[REG2:[0-9]+]], [[REG]], 12
-; CHECK: lxsiwax [[REG0:[0-9]+]], 0, [[REG2]]
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC2 at toc@ha
+; CHECK: ld r[[REG]], .LC2 at toc@l(r[[REG]])
+; CHECK: addi r[[REG2:[0-9]+]], r[[REG]], 12
+; CHECK: lxsiwax v[[REG0:[0-9]+]], 0, r[[REG2]]
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -200,9 +200,9 @@ entry:
; CHECK-LABEL: uwConv2qp
; CHECK-NOT: lwz
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -216,9 +216,9 @@ entry:
; CHECK-LABEL: uwConv2qp_02
; CHECK-NOT: lwz
-; CHECK: lxsiwzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsiwzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -232,12 +232,12 @@ entry:
ret void
; CHECK-LABEL: uwConv2qp_03
-; CHECK: addis [[REG:[0-9]+]], 2, .LC3 at toc@ha
-; CHECK-NEXT: ld [[REG]], .LC3 at toc@l([[REG]])
-; CHECK-NEXT: addi [[REG2:[0-9]+]], [[REG]], 12
-; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG2]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC3 at toc@ha
+; CHECK-NEXT: ld r[[REG]], .LC3 at toc@l(r[[REG]])
+; CHECK-NEXT: addi r[[REG2:[0-9]+]], r[[REG]], 12
+; CHECK-NEXT: lxsiwzx v[[REG1:[0-9]+]], 0, r[[REG2]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG1]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -252,11 +252,11 @@ entry:
ret void
; CHECK-LABEL: uwConv2qp_04
-; CHECK: lwz [[REG:[0-9]+]], 0(5)
-; CHECK-NEXT: add [[REG1:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: mtvsrwz [[REG0:[0-9]+]], [[REG1]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lwz r[[REG:[0-9]+]], 0(r5)
+; CHECK-NEXT: add r[[REG1:[0-9]+]], r[[REG]], r[[REG1]]
+; CHECK-NEXT: mtvsrwz v[[REG0:[0-9]+]], r[[REG1]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -269,9 +269,9 @@ entry:
; CHECK-LABEL: uhwConv2qp
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -284,9 +284,9 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_02
-; CHECK: lxsihzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsihzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -300,12 +300,12 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC4 at toc@ha
-; CHECK: ld [[REG0]], .LC4 at toc@l([[REG0]])
-; CHECK: addi [[REG0]], [[REG0]], 6
-; CHECK: lxsihzx [[REG:[0-9]+]], 0, [[REG0]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC4 at toc@ha
+; CHECK: ld r[[REG0]], .LC4 at toc@l(r[[REG0]])
+; CHECK: addi r[[REG0]], r[[REG0]], 6
+; CHECK: lxsihzx v[[REG:[0-9]+]], 0, r[[REG0]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -322,11 +322,11 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_04
-; CHECK: lhz [[REG0:[0-9]+]], 0(5)
-; CHECK: add 4, [[REG0]], 4
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lhz r[[REG0:[0-9]+]], 0(r5)
+; CHECK: add r4, r[[REG0]], r4
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -338,9 +338,9 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -353,9 +353,9 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_02
-; CHECK: lxsibzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsibzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -369,12 +369,12 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC5 at toc@ha
-; CHECK: ld [[REG0]], .LC5 at toc@l([[REG0]])
-; CHECK: addi [[REG0]], [[REG0]], 2
-; CHECK: lxsibzx [[REG:[0-9]+]], 0, [[REG0]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC5 at toc@ha
+; CHECK: ld r[[REG0]], .LC5 at toc@l(r[[REG0]])
+; CHECK: addi r[[REG0]], r[[REG0]], 2
+; CHECK: lxsibzx v[[REG:[0-9]+]], 0, r[[REG0]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -391,11 +391,11 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_04
-; CHECK: lbz [[REG0:[0-9]+]], 0(5)
-; CHECK: add 4, [[REG0]], 4
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lbz r[[REG0:[0-9]+]], 0(r5)
+; CHECK: add r4, r[[REG0]], r4
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -412,9 +412,9 @@ entry:
define double @qpConv2dp(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2dp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: xxlor 1, 2, 2
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: xxlor f1, v2, v2
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -426,11 +426,11 @@ entry:
define void @qpConv2dp_02(double* nocapture %res) {
; CHECK-LABEL: qpConv2dp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC6 at toc@ha
-; CHECK-NEXT: ld 4, .LC6 at toc@l(4)
-; CHECK-NEXT: lxvx 2, 0, 4
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsd 2, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC6 at toc@ha
+; CHECK-NEXT: ld r4, .LC6 at toc@l(r4)
+; CHECK-NEXT: lxvx v2, 0, r4
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* @f128global, align 16
@@ -443,12 +443,12 @@ entry:
define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2dp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 5, 2, .LC7 at toc@ha
-; CHECK-NEXT: sldi 4, 4, 3
-; CHECK-NEXT: ld 5, .LC7 at toc@l(5)
-; CHECK-NEXT: lxvx 2, 0, 5
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsdx 2, 3, 4
+; CHECK-NEXT: addis r5, r2, .LC7 at toc@ha
+; CHECK-NEXT: sldi r4, r4, 3
+; CHECK-NEXT: ld r5, .LC7 at toc@l(r5)
+; CHECK-NEXT: lxvx v2, 0, r5
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
@@ -463,11 +463,11 @@ entry:
define void @qpConv2dp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, double* nocapture %res) {
; CHECK-LABEL: qpConv2dp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsd 2, 0(5)
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -484,9 +484,9 @@ entry:
define float @qpConv2sp(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 1, 2
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f1, v2
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -498,12 +498,12 @@ entry:
define void @qpConv2sp_02(float* nocapture %res) {
; CHECK-LABEL: qpConv2sp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC6 at toc@ha
-; CHECK-NEXT: ld 4, .LC6 at toc@l(4)
-; CHECK-NEXT: lxvx 2, 0, 4
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfs 0, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC6 at toc@ha
+; CHECK-NEXT: ld r4, .LC6 at toc@l(r4)
+; CHECK-NEXT: lxvx v2, 0, r4
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* @f128global, align 16
@@ -516,13 +516,13 @@ entry:
define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2sp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 5, 2, .LC7 at toc@ha
-; CHECK-NEXT: sldi 4, 4, 2
-; CHECK-NEXT: ld 5, .LC7 at toc@l(5)
-; CHECK-NEXT: lxv 2, 48(5)
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfsx 0, 3, 4
+; CHECK-NEXT: addis r5, r2, .LC7 at toc@ha
+; CHECK-NEXT: sldi r4, r4, 2
+; CHECK-NEXT: ld r5, .LC7 at toc@l(r5)
+; CHECK-NEXT: lxv v2, 48(r5)
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfsx f0, r3, r4
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
@@ -537,12 +537,12 @@ entry:
define void @qpConv2sp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, float* nocapture %res) {
; CHECK-LABEL: qpConv2sp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfs 0, 0(5)
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfs f0, 0(r5)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -559,8 +559,8 @@ entry:
define fp128 @dpConv2qp(double %a) {
; CHECK-LABEL: dpConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -571,11 +571,11 @@ entry:
define void @dpConv2qp_02(double* nocapture readonly %a) {
; CHECK-LABEL: dpConv2qp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxsd 2, 0(3)
-; CHECK-NEXT: addis 3, 2, .LC8 at toc@ha
-; CHECK-NEXT: ld 3, .LC8 at toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: lxsd v2, 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC8 at toc@ha
+; CHECK-NEXT: ld r3, .LC8 at toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load double, double* %a, align 8
@@ -588,12 +588,12 @@ entry:
define void @dpConv2qp_02b(double* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: dpConv2qp_02b:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sldi 4, 4, 3
-; CHECK-NEXT: lxsdx 2, 3, 4
-; CHECK-NEXT: addis 3, 2, .LC8 at toc@ha
-; CHECK-NEXT: ld 3, .LC8 at toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: sldi r4, r4, 3
+; CHECK-NEXT: lxsdx v2, r3, r4
+; CHECK-NEXT: addis r3, r2, .LC8 at toc@ha
+; CHECK-NEXT: ld r3, .LC8 at toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%idxprom = sext i32 %idx to i64
@@ -608,10 +608,10 @@ entry:
define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) {
; CHECK-LABEL: dpConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: sldi 4, 4, 4
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 3, 4
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: sldi r4, r4, 4
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -625,9 +625,9 @@ entry:
define void @dpConv2qp_04(double %a, fp128* nocapture %res) {
; CHECK-LABEL: dpConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -639,8 +639,8 @@ entry:
define fp128 @spConv2qp(float %a) {
; CHECK-LABEL: spConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -651,11 +651,11 @@ entry:
define void @spConv2qp_02(float* nocapture readonly %a) {
; CHECK-LABEL: spConv2qp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxssp 2, 0(3)
-; CHECK-NEXT: addis 3, 2, .LC8 at toc@ha
-; CHECK-NEXT: ld 3, .LC8 at toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: lxssp v2, 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC8 at toc@ha
+; CHECK-NEXT: ld r3, .LC8 at toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load float, float* %a, align 4
@@ -668,12 +668,12 @@ entry:
define void @spConv2qp_02b(float* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: spConv2qp_02b:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sldi 4, 4, 2
-; CHECK-NEXT: lxsspx 2, 3, 4
-; CHECK-NEXT: addis 3, 2, .LC8 at toc@ha
-; CHECK-NEXT: ld 3, .LC8 at toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: sldi r4, r4, 2
+; CHECK-NEXT: lxsspx v2, r3, r4
+; CHECK-NEXT: addis r3, r2, .LC8 at toc@ha
+; CHECK-NEXT: ld r3, .LC8 at toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%idxprom = sext i32 %idx to i64
@@ -688,10 +688,10 @@ entry:
define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) {
; CHECK-LABEL: spConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: sldi 4, 4, 4
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 3, 4
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: sldi r4, r4, 4
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -705,9 +705,9 @@ entry:
define void @spConv2qp_04(float %a, fp128* nocapture %res) {
; CHECK-LABEL: spConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -721,10 +721,10 @@ entry:
define void @cvdp2sw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2sw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxws 2, 1
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxws v2, f1
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi double %val to i32
@@ -737,9 +737,9 @@ entry:
define void @cvdp2sdw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2sdw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxds 2, 1
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxds v2, f1
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi double %val to i64
@@ -752,10 +752,10 @@ entry:
define void @cvsp2sw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2sw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxws 2, 1
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxws v2, f1
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi float %val to i32
@@ -768,9 +768,9 @@ entry:
define void @cvsp2sdw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2sdw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxds 2, 1
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxds v2, f1
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi float %val to i64
@@ -783,10 +783,10 @@ entry:
define void @cvdp2uw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2uw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxws 0, 1
-; CHECK-NEXT: xxextractuw 2, 0, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxws f0, f1
+; CHECK-NEXT: xxextractuw v2, vs0, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui double %val to i32
@@ -799,9 +799,9 @@ entry:
define void @cvdp2udw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2udw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxds 2, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxds v2, f1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui double %val to i64
@@ -814,10 +814,10 @@ entry:
define void @cvsp2uw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2uw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxws 0, 1
-; CHECK-NEXT: xxextractuw 2, 0, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxws f0, f1
+; CHECK-NEXT: xxextractuw v2, vs0, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui float %val to i32
@@ -830,9 +830,9 @@ entry:
define void @cvsp2udw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2udw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxds 2, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxds v2, f1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui float %val to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-fma.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-fma.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-fma.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-fma.ll Thu Jul 12 13:18:57 2018
@@ -1,5 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
@@ -12,11 +13,11 @@ entry:
ret void
; CHECK-LABEL: qpFmadd
; CHECK-NOT: bl fmal
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsmaddqp [[REG5]], [[REG3]], [[REG4]]
-; CHECK-NEXT: stxv [[REG5]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
@@ -35,11 +36,11 @@ entry:
ret void
; CHECK-LABEL: qpFmadd_02
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsmaddqp [[REG3]], [[REG4]], [[REG5]]
-; CHECK-NEXT: stxv [[REG3]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
+; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
@@ -57,11 +58,11 @@ entry:
ret void
; CHECK-LABEL: qpFmadd_03
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsmaddqp [[REG5]], [[REG3]], [[REG4]]
-; CHECK-NEXT: stxv [[REG5]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
@@ -80,11 +81,11 @@ entry:
ret void
; CHECK-LABEL: qpFnmadd
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsnmaddqp [[REG3]], [[REG4]], [[REG5]]
-; CHECK-NEXT: stxv [[REG3]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
+; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
@@ -103,11 +104,11 @@ entry:
ret void
; CHECK-LABEL: qpFnmadd_02
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsnmaddqp [[REG5]], [[REG3]], [[REG4]]
-; CHECK-NEXT: stxv [[REG5]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsnmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
@@ -125,11 +126,11 @@ entry:
ret void
; CHECK-LABEL: qpFmsub
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsnmsubqp [[REG3]], [[REG5]], [[REG4]]
-; CHECK-NEXT: stxv [[REG3]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsnmsubqp v[[REG3]], v[[REG5]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
@@ -147,11 +148,11 @@ entry:
ret void
; CHECK-LABEL: qpFmsub_02
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsmsubqp [[REG5]], [[REG3]], [[REG4]]
-; CHECK-NEXT: stxv [[REG5]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsmsubqp v[[REG5]], v[[REG3]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
@@ -170,12 +171,12 @@ entry:
ret void
; CHECK-LABEL: qpFnmsub
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsnegqp [[REG4]], [[REG4]]
-; CHECK: xsnmaddqp [[REG3]], [[REG4]], [[REG5]]
-; CHECK-NEXT: stxv [[REG3]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsnegqp v[[REG4]], v[[REG4]]
+; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
+; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
@@ -194,10 +195,10 @@ entry:
ret void
; CHECK-LABEL: qpFnmsub_02
; CHECK-NOT: bl __multf3
-; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
-; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
-; CHECK: xsnmsubqp [[REG5]], [[REG3]], [[REG4]]
-; CHECK-NEXT: stxv [[REG5]], 0(6)
+; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
+; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
+; CHECK: xsnmsubqp v[[REG5]], v[[REG3]], v[[REG4]]
+; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-passByValue.ll Thu Jul 12 13:18:57 2018
@@ -1,14 +1,14 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
; Function Attrs: norecurse nounwind readnone
define fp128 @loadConstant() {
; CHECK-LABEL: loadConstant:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis [[REG0:[0-9]+]], 2, .LCPI0_0 at toc@ha
-; CHECK-NEXT: addi [[REG0]], [[REG0]], .LCPI0_0 at toc@l
-; CHECK-NEXT: lxvx 2, 0, [[REG0]]
+; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI0_0 at toc@ha
+; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI0_0 at toc@l
+; CHECK-NEXT: lxvx v2, 0, r[[REG0]]
; CHECK-NEXT: blr
entry:
ret fp128 0xL00000000000000004001400000000000
@@ -18,11 +18,11 @@ define fp128 @loadConstant() {
define fp128 @loadConstant2(fp128 %a, fp128 %b) {
; CHECK-LABEL: loadConstant2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: addis [[REG0:[0-9]+]], 2, .LCPI1_0 at toc@ha
-; CHECK-NEXT: addi [[REG0]], [[REG0]], .LCPI1_0 at toc@l
-; CHECK-NEXT: lxvx [[REG0]], 0, [[REG0]]
-; CHECK-NEXT: xsaddqp 2, 2, [[REG0]]
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI1_0 at toc@ha
+; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI1_0 at toc@l
+; CHECK-NEXT: lxvx v[[REG1:[0-9]+]], 0, r[[REG0]]
+; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -35,9 +35,9 @@ define fp128 @loadConstant2(fp128 %a, fp
define signext i32 @fp128Param(fp128 %a) {
; CHECK-LABEL: fp128Param:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%conv = fptosi fp128 %a to i32
@@ -49,7 +49,7 @@ entry:
define fp128 @fp128Return(fp128 %a, fp128 %b) {
; CHECK-LABEL: fp128Return:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsaddqp 2, 2, 3
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -61,11 +61,11 @@ entry:
define fp128 @fp128Array(fp128* nocapture readonly %farray,
; CHECK-LABEL: fp128Array:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sldi 4, 4, 4
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: add 4, 3, 4
-; CHECK-NEXT: lxv 3, -16(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
+; CHECK-NEXT: sldi r4, r4, 4
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: add r4, r3, r4
+; CHECK-NEXT: lxv v3, -16(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
i32 signext %loopcnt, fp128* nocapture readnone %sum) {
entry:
@@ -84,19 +84,19 @@ entry:
define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-LABEL: maxVecParam:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: lxv [[REG0:[0-9]+]], 224(1)
-; CHECK-NEXT: xsaddqp 2, 2, 4
-; CHECK-NEXT: xsaddqp 2, 2, 5
-; CHECK-NEXT: xsaddqp 2, 2, 6
-; CHECK-NEXT: xsaddqp 2, 2, 7
-; CHECK-NEXT: xsaddqp 2, 2, 8
-; CHECK-NEXT: xsaddqp 2, 2, 9
-; CHECK-NEXT: xsaddqp 2, 2, 10
-; CHECK-NEXT: xsaddqp 2, 2, 11
-; CHECK-NEXT: xsaddqp 2, 2, 12
-; CHECK-NEXT: xsaddqp 2, 2, 13
-; CHECK-NEXT: xssubqp 2, 2, [[REG0]]
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
+; CHECK-NEXT: xsaddqp v2, v2, v4
+; CHECK-NEXT: xsaddqp v2, v2, v5
+; CHECK-NEXT: xsaddqp v2, v2, v6
+; CHECK-NEXT: xsaddqp v2, v2, v7
+; CHECK-NEXT: xsaddqp v2, v2, v8
+; CHECK-NEXT: xsaddqp v2, v2, v9
+; CHECK-NEXT: xsaddqp v2, v2, v10
+; CHECK-NEXT: xsaddqp v2, v2, v11
+; CHECK-NEXT: xsaddqp v2, v2, v12
+; CHECK-NEXT: xsaddqp v2, v2, v13
+; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr
fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
fp128 %p11, fp128 %p12, fp128 %p13) {
@@ -121,10 +121,10 @@ entry:
define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrwa 4, 5
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvsdqp [[REG0:[0-9]+]], 4
-; CHECK-NEXT: xsaddqp 2, 2, [[REG0]]
+; CHECK-NEXT: mtvsrwa v4, r5
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvsdqp v[[REG0:[0-9]+]], v4
+; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -136,10 +136,10 @@ entry:
define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
; CHECK-LABEL: mixParam_01f:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrwa [[REG0:[0-9]+]], 3
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvsdqp [[REG1:[0-9]+]], [[REG0]]
-; CHECK-NEXT: xsaddqp 2, 2, [[REG1]]
+; CHECK-NEXT: mtvsrwa v[[REG0:[0-9]+]], r3
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvsdqp v[[REG1:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
; CHECK-NEXT: blr
entry:
%add = fadd fp128 %a, %b
@@ -152,17 +152,17 @@ entry:
define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: lwz 3, 96(1)
-; CHECK: add 4, 7, 9
-; CHECK-NEXT: xxlor [[REG0:[0-9]+]], 1, 1
-; CHECK-DAG: add 4, 4, 10
-; CHECK: xscvdpqp [[REG0]], [[REG0]]
-; CHECK-NEXT: add 3, 4, 3
-; CHECK-NEXT: clrldi 3, 3, 32
-; CHECK-NEXT: std 3, 0(6)
-; CHECK-NEXT: lxv [[REG1:[0-9]+]], 0(8)
-; CHECK-NEXT: xsaddqp 2, [[REG1]], 2
-; CHECK-NEXT: xsaddqp 2, 2, 3
+; CHECK-DAG: lwz r3, 96(r1)
+; CHECK: add r4, r7, r9
+; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-DAG: add r4, r4, r10
+; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
+; CHECK-NEXT: add r3, r4, r3
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: std r3, 0(r6)
+; CHECK-NEXT: lxv v[[REG1:[0-9]+]], 0(r8)
+; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
+; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
@@ -185,16 +185,16 @@ entry:
define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02f:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: add 4, 4, 6
-; CHECK-NEXT: xxlor [[REG0:[0-9]+]], 1, 1
-; CHECK-NEXT: add 4, 4, 7
-; CHECK-NEXT: xscvdpqp [[REG0]], [[REG0]]
-; CHECK-NEXT: add 4, 4, 8
-; CHECK-NEXT: clrldi 4, 4, 32
-; CHECK-NEXT: std 4, 0(3)
-; CHECK-NEXT: lxv [[REG1:[0-9]+]], 0(5)
-; CHECK-NEXT: xsaddqp 2, [[REG1]], 2
-; CHECK-NEXT: xsaddqp 2, 2, [[REG0]]
+; CHECK-NEXT: add r4, r4, r6
+; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT: add r4, r4, r7
+; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
+; CHECK-NEXT: add r4, r4, r8
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: std r4, 0(r3)
+; CHECK-NEXT: lxv v[[REG1:[0-9]+]], 0(r5)
+; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
+; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr
i16 signext %p4, fp128* nocapture readonly %p5,
i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
@@ -218,15 +218,15 @@ entry:
define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: ld 3, 104(1)
-; CHECK-DAG: mtvsrwa [[REG2:[0-9]+]], 10
-; CHECK-DAG: stxv 2, 0(9)
-; CHECK-DAG: xscvsdqp [[REG1:[0-9]+]], [[REG2]]
-; CHECK: stxvx 3, 0, 3
-; CHECK-NEXT: lxv 2, 0(9)
-; CHECK-NEXT: xsaddqp 2, 2, [[REG1]]
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsd 2, 0(5)
+; CHECK-DAG: ld r3, 104(r1)
+; CHECK-DAG: mtvsrwa v[[REG2:[0-9]+]], r10
+; CHECK-DAG: stxv v2, 0(r9)
+; CHECK-DAG: xscvsdqp v[[REG1:[0-9]+]], v[[REG2]]
+; CHECK: stxvx v3, 0, r3
+; CHECK-NEXT: lxv v2, 0(r9)
+; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
<4 x i32>* nocapture %vec2) {
@@ -245,14 +245,14 @@ entry:
define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03f:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mtvsrwa [[REG0:[0-9]+]], 5
-; CHECK-NEXT: stxv [[REG1:[0-9]+]], 0(4)
-; CHECK-NEXT: stxv [[REG2:[0-9]+]], 0(7)
-; CHECK-NEXT: lxv [[REG1]], 0(4)
-; CHECK-NEXT: xscvsdqp [[REG3:[0-9]+]], [[REG0]]
-; CHECK-NEXT: xsaddqp [[REG4:[0-9]+]], [[REG1]], [[REG3]]
-; CHECK-NEXT: xscvqpdp 2, [[REG4]]
-; CHECK-NEXT: stxsd 2, 0(3)
+; CHECK-NEXT: mtvsrwa v[[REG0:[0-9]+]], r5
+; CHECK-NEXT: stxv v[[REG1:[0-9]+]], 0(r4)
+; CHECK-NEXT: stxv v[[REG2:[0-9]+]], 0(r7)
+; CHECK-NEXT: lxv v[[REG1]], 0(r4)
+; CHECK-NEXT: xscvsdqp v[[REG3:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: xsaddqp v[[REG4:[0-9]+]], v[[REG1]], v[[REG3]]
+; CHECK-NEXT: xscvqpdp v2, v[[REG4]]
+; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
<4 x i32>* nocapture %vec2) {
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-rounding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-rounding.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-rounding.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-rounding.ll Thu Jul 12 13:18:57 2018
@@ -1,5 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define void @qp_trunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
@@ -9,7 +10,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_trunc
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 1
; CHECK: blr
}
declare fp128 @llvm.trunc.f128(fp128 %Val)
@@ -21,7 +22,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_rint
-; CHECK: xsrqpix 0, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpix 0, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.rint.f128(fp128 %Val)
@@ -33,7 +34,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_nearbyint
-; CHECK: xsrqpi 0, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpi 0, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.nearbyint.f128(fp128 %Val)
@@ -45,7 +46,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_round
-; CHECK: xsrqpi 0, {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: xsrqpi 0, v{{[0-9]+}}, v{{[0-9]+}}, 0
; CHECK: blr
}
declare fp128 @llvm.round.f128(fp128 %Val)
@@ -57,7 +58,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_floor
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.floor.f128(fp128 %Val)
@@ -69,7 +70,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_ceil
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 2
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 2
; CHECK: blr
}
declare fp128 @llvm.ceil.f128(fp128 %Val)
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll Thu Jul 12 13:18:57 2018
@@ -1,6 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
-; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
fp128 0xLF000000000000000400808AB851EB851,
@@ -16,9 +16,9 @@ entry:
ret i64 %conv
; CHECK-LABEL: qpConv2sdw
-; CHECK: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: mfvsrd 3, [[CONV]]
+; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr
}
@@ -33,11 +33,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2sdw_02
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
-; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxsd [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
+; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsd v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -53,13 +53,13 @@ entry:
ret i64 %conv
; CHECK-LABEL: qpConv2sdw_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: mfvsrd 3, [[CONV]]
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK-DAG: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr
}
@@ -75,11 +75,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2sdw_04
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxsd [[CONV]], 0(5)
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsd v[[CONV]], 0(r5)
; CHECK-NEXT: blr
}
@@ -96,8 +96,8 @@ entry:
ret void
; CHECK-LABEL: qpConv2sdw_testXForm
-; CHECK: xscvqpsdz [[CONV:[0-9]+]],
-; CHECK-NEXT: stxsdx [[CONV]], 3, 4
+; CHECK: xscvqpsdz v[[CONV:[0-9]+]],
+; CHECK-NEXT: stxsdx v[[CONV]], r3, r4
; CHECK-NEXT: blr
}
@@ -109,9 +109,9 @@ entry:
ret i64 %conv
; CHECK-LABEL: qpConv2udw
-; CHECK: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: mfvsrd 3, [[CONV]]
+; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr
}
@@ -126,11 +126,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2udw_02
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
-; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxsd [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
+; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsd v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -146,13 +146,13 @@ entry:
ret i64 %conv
; CHECK-LABEL: qpConv2udw_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: mfvsrd 3, [[CONV]]
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK-DAG: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrd r3, v[[CONV]]
; CHECK-NEXT: blr
}
@@ -168,11 +168,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2udw_04
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK: xsaddqp [[REG]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxsd [[CONV]], 0(5)
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsd v[[CONV]], 0(r5)
; CHECK-NEXT: blr
}
@@ -189,8 +189,8 @@ entry:
ret void
; CHECK-LABEL: qpConv2udw_testXForm
-; CHECK: xscvqpudz [[CONV:[0-9]+]],
-; CHECK-NEXT: stxsdx [[CONV]], 3, 4
+; CHECK: xscvqpudz v[[CONV:[0-9]+]],
+; CHECK-NEXT: stxsdx v[[CONV]], r3, r4
; CHECK-NEXT: blr
}
@@ -202,10 +202,10 @@ entry:
ret i32 %conv
; CHECK-LABEL: qpConv2sw
-; CHECK: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
-; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
+; CHECK-NEXT: extsw r3, r[[REG2]]
; CHECK-NEXT: blr
}
@@ -220,11 +220,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2sw_02
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
-; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
+; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3
; CHECK-NEXT: blr
}
@@ -240,14 +240,14 @@ entry:
ret i32 %conv
; CHECK-LABEL: qpConv2sw_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
-; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK-DAG: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]]
+; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
+; CHECK-NEXT: extsw r3, r[[REG2]]
; CHECK-NEXT: blr
}
@@ -263,11 +263,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2sw_04
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]]
+; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5
; CHECK-NEXT: blr
}
@@ -279,9 +279,9 @@ entry:
ret i32 %conv
; CHECK-LABEL: qpConv2uw
-; CHECK: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
; CHECK: blr
}
@@ -296,11 +296,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2uw_02
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
-; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]])
+; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3
; CHECK: blr
}
@@ -316,13 +316,13 @@ entry:
ret i32 %conv
; CHECK-LABEL: qpConv2uw_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
-; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0 at toc@ha
+; CHECK-DAG: ld r[[REG0]], .LC0 at toc@l(r[[REG0]])
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]])
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]]
+; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
; CHECK: blr
}
@@ -338,11 +338,11 @@ entry:
ret void
; CHECK-LABEL: qpConv2uw_04
-; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
-; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
-; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
-; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4)
+; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3)
+; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]]
+; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]]
+; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5
; CHECK: blr
}
@@ -352,10 +352,10 @@ entry:
define signext i16 @qpConv2shw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: extsh 3, 3
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: extsh r3, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -367,11 +367,11 @@ entry:
define void @qpConv2shw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2shw_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 2, 32(4)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: stxsihx 2, 0, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v2, 32(r4)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: stxsihx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
@@ -386,14 +386,14 @@ entry:
define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 3, 16(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: extsh 3, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: extsh r3, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -410,11 +410,11 @@ define void @qpConv2shw_04(fp128* nocapt
fp128* nocapture readonly %b, i16* nocapture %res) {
; CHECK-LABEL: qpConv2shw_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: stxsihx 2, 0, 5
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: stxsihx v2, 0, r5
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -429,10 +429,10 @@ entry:
define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -444,11 +444,11 @@ entry:
define void @qpConv2uhw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2uhw_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 2, 32(4)
-; CHECK-NEXT: xscvqpuwz 2, 2
-; CHECK-NEXT: stxsihx 2, 0, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v2, 32(r4)
+; CHECK-NEXT: xscvqpuwz v2, v2
+; CHECK-NEXT: stxsihx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
@@ -463,14 +463,14 @@ entry:
define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 3, 16(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -487,11 +487,11 @@ define void @qpConv2uhw_04(fp128* nocapt
fp128* nocapture readonly %b, i16* nocapture %res) {
; CHECK-LABEL: qpConv2uhw_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpuwz 2, 2
-; CHECK-NEXT: stxsihx 2, 0, 5
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpuwz v2, v2
+; CHECK-NEXT: stxsihx v2, 0, r5
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -506,10 +506,10 @@ entry:
define signext i8 @qpConv2sb(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: extsb 3, 3
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: extsb r3, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -521,11 +521,11 @@ entry:
define void @qpConv2sb_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2sb_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 2, 32(4)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: stxsibx 2, 0, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v2, 32(r4)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: stxsibx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
@@ -540,14 +540,14 @@ entry:
define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 3, 16(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: extsb 3, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: extsb r3, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -564,11 +564,11 @@ define void @qpConv2sb_04(fp128* nocaptu
fp128* nocapture readonly %b, i8* nocapture %res) {
; CHECK-LABEL: qpConv2sb_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: stxsibx 2, 0, 5
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: stxsibx v2, 0, r5
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -583,10 +583,10 @@ entry:
define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -598,11 +598,11 @@ entry:
define void @qpConv2ub_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2ub_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 2, 32(4)
-; CHECK-NEXT: xscvqpuwz 2, 2
-; CHECK-NEXT: stxsibx 2, 0, 3
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v2, 32(r4)
+; CHECK-NEXT: xscvqpuwz v2, v2
+; CHECK-NEXT: stxsibx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds
@@ -617,14 +617,14 @@ entry:
define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxv 3, 16(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpswz 2, 2
-; CHECK-NEXT: mfvsrwz 3, 2
-; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxv v3, 16(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpswz v2, v2
+; CHECK-NEXT: mfvsrwz r3, v2
+; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -641,11 +641,11 @@ define void @qpConv2ub_04(fp128* nocaptu
fp128* nocapture readonly %b, i8* nocapture %res) {
; CHECK-LABEL: qpConv2ub_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpuwz 2, 2
-; CHECK-NEXT: stxsibx 2, 0, 5
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpuwz v2, v2
+; CHECK-NEXT: stxsibx v2, 0, r5
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll?rev=336940&r1=336939&r2=336940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll Thu Jul 12 13:18:57 2018
@@ -1,9 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | \
-; RUN: FileCheck %s -check-prefix=CHECK-BE
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
+; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
+; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE
; Vector extract DWord and convert to quad precision.
@@ -14,14 +15,14 @@
define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
; CHECK-LABEL: sdwVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltd 34, 34, 1
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxspltd v2, v2, 1
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: sdwVecConv2qp:
-; CHECK-BE: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <2 x i64> %b, i32 0
@@ -34,15 +35,15 @@ entry:
define void @sdwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
; CHECK-LABEL: sdwVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: sdwVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxspltd 34, 34, 1
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: xxspltd v2, v2, 1
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <2 x i64> %b, i32 1
@@ -55,11 +56,11 @@ entry:
define void @sdwVecConv2qp_02(fp128* nocapture %a) {
; CHECK-LABEL: sdwVecConv2qp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
-; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
-; CHECK-NEXT: lxsd 2, 0(4)
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: lxsd v2, 0(r4)
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load <2 x i64>, <2 x i64>* @sdwVecMem, align 16
@@ -73,9 +74,9 @@ entry:
define void @sdwVecConv2qp1_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
; CHECK-LABEL: sdwVecConv2qp1_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxsd 2, 8(4)
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: lxsd v2, 8(r4)
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load <2 x i64>, <2 x i64>* %b, align 16
@@ -89,15 +90,15 @@ entry:
define void @udwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
; CHECK-LABEL: udwVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltd 34, 34, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxspltd v2, v2, 1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: udwVecConv2qp:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <2 x i64> %b, i32 0
@@ -110,15 +111,15 @@ entry:
define void @udwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
; CHECK-LABEL: udwVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: udwVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxspltd 34, 34, 1
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: xxspltd v2, v2, 1
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <2 x i64> %b, i32 1
@@ -131,11 +132,11 @@ entry:
define void @udwVecConv2qp1_02(fp128* nocapture %a) {
; CHECK-LABEL: udwVecConv2qp1_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC1 at toc@ha
-; CHECK-NEXT: ld 4, .LC1 at toc@l(4)
-; CHECK-NEXT: lxsd 2, 8(4)
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC1 at toc@ha
+; CHECK-NEXT: ld r4, .LC1 at toc@l(r4)
+; CHECK-NEXT: lxsd v2, 8(r4)
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load <2 x i64>, <2 x i64>* @udwVecMem, align 16
@@ -149,9 +150,9 @@ entry:
define void @udwVecConv2qp_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
; CHECK-LABEL: udwVecConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxsd 2, 0(4)
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: lxsd v2, 0(r4)
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load <2 x i64>, <2 x i64>* %b, align 16
@@ -167,17 +168,17 @@ entry:
define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vspltw 2, 2, 3
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vspltw v2, v2, 3
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp:
-; CHECK-BE: vspltw 2, 2, 0
-; CHECK-BE-NEXT: vextsw2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: vspltw v2, v2, 0
+; CHECK-BE-NEXT: vextsw2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 0
@@ -190,16 +191,16 @@ entry:
define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vspltw 2, 2, 2
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vspltw v2, v2, 2
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp1:
-; CHECK-BE: vextsw2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: vextsw2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 1
@@ -212,16 +213,16 @@ entry:
define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp2:
-; CHECK-BE: vspltw 2, 2, 2
-; CHECK-BE-NEXT: vextsw2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: vspltw v2, v2, 2
+; CHECK-BE-NEXT: vextsw2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 2
@@ -234,17 +235,17 @@ entry:
define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vspltw 2, 2, 0
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vspltw v2, v2, 0
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp3:
-; CHECK-BE: vspltw 2, 2, 3
-; CHECK-BE-NEXT: vextsw2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: vspltw v2, v2, 3
+; CHECK-BE-NEXT: vextsw2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 3
@@ -257,15 +258,15 @@ entry:
define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxextractuw 34, 34, 12
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxextractuw v2, v2, 12
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp:
-; CHECK-BE: xxextractuw 34, 34, 0
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: xxextractuw v2, v2, 0
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 0
@@ -278,15 +279,15 @@ entry:
define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxextractuw 34, 34, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxextractuw v2, v2, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp1:
-; CHECK-BE: xxextractuw 34, 34, 4
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: xxextractuw v2, v2, 4
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 1
@@ -299,15 +300,15 @@ entry:
define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxextractuw 34, 34, 4
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxextractuw v2, v2, 4
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp2:
-; CHECK-BE: xxextractuw 34, 34, 8
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: xxextractuw v2, v2, 8
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 2
@@ -320,15 +321,15 @@ entry:
define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxextractuw 34, 34, 0
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: xxextractuw v2, v2, 0
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp3:
-; CHECK-BE: xxextractuw 34, 34, 12
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE: xxextractuw v2, v2, 12
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 3
@@ -343,18 +344,18 @@ entry:
define void @shwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 14
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 14
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 0
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 0
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 0
@@ -367,18 +368,18 @@ entry:
define void @shwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 12
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 12
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 2
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 2
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 1
@@ -391,18 +392,18 @@ entry:
define void @shwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 10
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 10
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 4
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 4
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 2
@@ -415,18 +416,18 @@ entry:
define void @shwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 8
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 8
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp3:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 6
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 6
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 3
@@ -439,18 +440,18 @@ entry:
define void @shwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp4:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 6
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 6
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp4:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 8
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 8
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 4
@@ -463,18 +464,18 @@ entry:
define void @shwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 4
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 4
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp5:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 10
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 10
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 5
@@ -487,18 +488,18 @@ entry:
define void @shwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp6:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 2
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 2
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp6:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 12
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 12
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 6
@@ -511,18 +512,18 @@ entry:
define void @shwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: shwVecConv2qp7:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 0
-; CHECK-NEXT: vextsh2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 0
+; CHECK-NEXT: vextsh2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: shwVecConv2qp7:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 14
-; CHECK-BE-NEXT: vextsh2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 14
+; CHECK-BE-NEXT: vextsh2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 7
@@ -535,16 +536,16 @@ entry:
define void @uhwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 14
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 14
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 0
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 0
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 0
@@ -557,16 +558,16 @@ entry:
define void @uhwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 12
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 12
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 2
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 2
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 1
@@ -579,16 +580,16 @@ entry:
define void @uhwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 10
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 10
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 4
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 4
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 2
@@ -601,16 +602,16 @@ entry:
define void @uhwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp3:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 6
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 6
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 3
@@ -623,16 +624,16 @@ entry:
define void @uhwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp4:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 6
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 6
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp4:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 8
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 8
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 4
@@ -645,16 +646,16 @@ entry:
define void @uhwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 4
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 4
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp5:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 10
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 10
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 5
@@ -667,16 +668,16 @@ entry:
define void @uhwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp6:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 2
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 2
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp6:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 12
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 12
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 6
@@ -689,16 +690,16 @@ entry:
define void @uhwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) {
; CHECK-LABEL: uhwVecConv2qp7:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractuh 2, 2, 0
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractuh v2, v2, 0
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: uhwVecConv2qp7:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractuh 2, 2, 14
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractuh v2, v2, 14
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %b, i32 7
@@ -713,18 +714,18 @@ entry:
define void @sbVecConv2qp(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 15
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 15
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 0
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 0
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 0
@@ -737,18 +738,18 @@ entry:
define void @sbVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 14
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 14
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 1
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 1
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 1
@@ -761,18 +762,18 @@ entry:
define void @sbVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 13
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 13
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 2
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 2
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 2
@@ -785,18 +786,18 @@ entry:
define void @sbVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 12
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 12
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp3:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 3
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 3
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 3
@@ -809,18 +810,18 @@ entry:
define void @sbVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp4:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 11
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 11
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp4:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 4
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 4
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 4
@@ -833,18 +834,18 @@ entry:
define void @sbVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 10
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 10
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp5:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 5
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 5
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 5
@@ -857,18 +858,18 @@ entry:
define void @sbVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp6:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 9
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 9
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp6:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 6
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 6
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 6
@@ -881,18 +882,18 @@ entry:
define void @sbVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp7:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 8
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 8
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp7:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 7
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 7
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 7
@@ -905,18 +906,18 @@ entry:
define void @sbVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 7
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 7
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp8:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 8
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 8
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 8
@@ -929,18 +930,18 @@ entry:
define void @sbVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp9:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 6
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 6
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp9:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 9
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 9
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 9
@@ -953,18 +954,18 @@ entry:
define void @sbVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp10:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 5
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 5
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp10:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 10
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 10
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 10
@@ -977,18 +978,18 @@ entry:
define void @sbVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp11:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 4
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 4
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp11:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 11
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 11
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 11
@@ -1001,18 +1002,18 @@ entry:
define void @sbVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp12:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 3
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 3
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp12:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 12
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 12
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 12
@@ -1025,18 +1026,18 @@ entry:
define void @sbVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp13:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 2
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 2
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp13:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 13
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 13
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 13
@@ -1049,18 +1050,18 @@ entry:
define void @sbVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp14:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 1
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 1
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp14:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 14
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 14
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 14
@@ -1073,18 +1074,18 @@ entry:
define void @sbVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: sbVecConv2qp15:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 0
-; CHECK-NEXT: vextsb2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 0
+; CHECK-NEXT: vextsb2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: sbVecConv2qp15:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 15
-; CHECK-BE-NEXT: vextsb2d 2, 2
-; CHECK-BE-NEXT: xscvsdqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 15
+; CHECK-BE-NEXT: vextsb2d v2, v2
+; CHECK-BE-NEXT: xscvsdqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 15
@@ -1097,16 +1098,16 @@ entry:
define void @ubVecConv2qp(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 15
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 15
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 0
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 0
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 0
@@ -1119,16 +1120,16 @@ entry:
define void @ubVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 14
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 14
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp1:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 1
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 1
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 1
@@ -1141,16 +1142,16 @@ entry:
define void @ubVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 13
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 13
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp2:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 2
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 2
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 2
@@ -1163,16 +1164,16 @@ entry:
define void @ubVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 12
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 12
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp3:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 3
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 3
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 3
@@ -1185,16 +1186,16 @@ entry:
define void @ubVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp4:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 11
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 11
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp4:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 4
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 4
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 4
@@ -1207,16 +1208,16 @@ entry:
define void @ubVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp5:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 10
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 10
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp5:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 5
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 5
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 5
@@ -1229,16 +1230,16 @@ entry:
define void @ubVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp6:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 9
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 9
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp6:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 6
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 6
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 6
@@ -1251,16 +1252,16 @@ entry:
define void @ubVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp7:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp7:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 7
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 7
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 7
@@ -1273,16 +1274,16 @@ entry:
define void @ubVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 7
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 7
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp8:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 8
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 8
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 8
@@ -1295,16 +1296,16 @@ entry:
define void @ubVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp9:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 6
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 6
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp9:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 9
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 9
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 9
@@ -1317,16 +1318,16 @@ entry:
define void @ubVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp10:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 5
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 5
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp10:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 10
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 10
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 10
@@ -1339,16 +1340,16 @@ entry:
define void @ubVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp11:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 4
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 4
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp11:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 11
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 11
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 11
@@ -1361,16 +1362,16 @@ entry:
define void @ubVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp12:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 3
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 3
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp12:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 12
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 12
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 12
@@ -1383,16 +1384,16 @@ entry:
define void @ubVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp13:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 2
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 2
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp13:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 13
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 13
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 13
@@ -1405,16 +1406,16 @@ entry:
define void @ubVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp14:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp14:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 14
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 14
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 14
@@ -1427,16 +1428,16 @@ entry:
define void @ubVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) {
; CHECK-LABEL: ubVecConv2qp15:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextractub 2, 2, 0
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 34, 0(3)
+; CHECK-NEXT: vextractub v2, v2, 0
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: ubVecConv2qp15:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: vextractub 2, 2, 15
-; CHECK-BE-NEXT: xscvudqp 2, 2
-; CHECK-BE-NEXT: stxv 34, 0(3)
+; CHECK-BE-NEXT: vextractub v2, v2, 15
+; CHECK-BE-NEXT: xscvudqp v2, v2
+; CHECK-BE-NEXT: stxv v2, 0(r3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %b, i32 15
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