[PATCH] D49255: AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

This improves code for the same reasons as scalarizing 32-bit
element vectors.


https://reviews.llvm.org/D49255

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/call-argument-types.ll
  test/CodeGen/AMDGPU/mad-mix-lo.ll
  test/CodeGen/AMDGPU/mul.i16.ll

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