[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

In general, looks good to me, but probably wait for someone else to review, too.

I'm assuming that you have run `ninja check-llvm-tools-llvm-mca-x86` and it was ok. (the test coverage seems to be ok as-is.)



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Comment at: lib/Target/X86/X86Schedule.td:122
+// Bit Test
+defm WriteBTr    : X86SchedWritePair;
+
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Hmm. Nits:
1. (not a nit) The suffix `r` notes that only the non-mem versions are covered.
   I wonder if we can convey that somehow better.
2. These cover 4 different bit-test instructions - `bt`,`bt[rcs]`
   Naming this `WriteBTr` //may// be confizing - is this only about `bt` instruction?
   How about calling it `WriteBitTest`?


https://reviews.llvm.org/D49243