[PATCH] D49218: [Sparc] Use the IntPair reg class for r constraints with value type f64

[Daniel Cederman via Phabricator via llvm-commits]

dcederman created this revision.
dcederman added reviewers: venkatra, jyknight.
Herald added subscribers: llvm-commits, jrtc27, fedor.sergeev, eraman.

This is how it appears to be handled in GCC and it prevents a "Unknown mismatch" error in the SelectionDAGBuilder.


Repository:
  rL LLVM

https://reviews.llvm.org/D49218

Files:
  lib/Target/Sparc/SparcISelLowering.cpp
  test/CodeGen/SPARC/inlineasm.ll


Index: test/CodeGen/SPARC/inlineasm.ll
===================================================================
--- test/CodeGen/SPARC/inlineasm.ll
+++ test/CodeGen/SPARC/inlineasm.ll
@@ -130,3 +130,12 @@
   tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
   ret void
 }
+
+; CHECK-LABEL: test_constraint_r_f64:
+; CHECK: std %o0, [%sp+96]
+; CHECK: ldd [%sp+96], %f0
+define double @test_constraint_r_f64() {
+entry:
+  %0 = call double asm sideeffect "", "=r"()
+  ret double %0
+}
Index: lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- lib/Target/Sparc/SparcISelLowering.cpp
+++ lib/Target/Sparc/SparcISelLowering.cpp
@@ -3508,7 +3508,7 @@
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
-      if (VT == MVT::v2i32)
+      if (VT == MVT::v2i32 || VT == MVT::f64)
         return std::make_pair(0U, &SP::IntPairRegClass);
       else
         return std::make_pair(0U, &SP::IntRegsRegClass);


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