[llvm] r336883 - [X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 11 20:42:42 PDT 2018
Author: ctopper
Date: Wed Jul 11 20:42:41 2018
New Revision: 336883
URL: http://llvm.org/viewvc/llvm-project?rev=336883&view=rev
Log:
[X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
We now use llvm.fma.f32/f64 or llvm.x86.fmadd.f32/f64 intrinsics that use scalar types rather than vector types. So we don't these special ISD nodes that operate on the lowest element of a vector.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrFMA.td
llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=336883&r1=336882&r2=336883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 11 20:42:41 2018
@@ -26055,22 +26055,6 @@ const char *X86TargetLowering::getTarget
case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
- case X86ISD::FMADDS1: return "X86ISD::FMADDS1";
- case X86ISD::FNMADDS1: return "X86ISD::FNMADDS1";
- case X86ISD::FMSUBS1: return "X86ISD::FMSUBS1";
- case X86ISD::FNMSUBS1: return "X86ISD::FNMSUBS1";
- case X86ISD::FMADDS1_RND: return "X86ISD::FMADDS1_RND";
- case X86ISD::FNMADDS1_RND: return "X86ISD::FNMADDS1_RND";
- case X86ISD::FMSUBS1_RND: return "X86ISD::FMSUBS1_RND";
- case X86ISD::FNMSUBS1_RND: return "X86ISD::FNMSUBS1_RND";
- case X86ISD::FMADDS3: return "X86ISD::FMADDS3";
- case X86ISD::FNMADDS3: return "X86ISD::FNMADDS3";
- case X86ISD::FMSUBS3: return "X86ISD::FMSUBS3";
- case X86ISD::FNMSUBS3: return "X86ISD::FNMSUBS3";
- case X86ISD::FMADDS3_RND: return "X86ISD::FMADDS3_RND";
- case X86ISD::FNMADDS3_RND: return "X86ISD::FNMADDS3_RND";
- case X86ISD::FMSUBS3_RND: return "X86ISD::FMSUBS3_RND";
- case X86ISD::FNMSUBS3_RND: return "X86ISD::FNMSUBS3_RND";
case X86ISD::VPMADD52H: return "X86ISD::VPMADD52H";
case X86ISD::VPMADD52L: return "X86ISD::VPMADD52L";
case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
@@ -37707,28 +37691,12 @@ static unsigned negateFMAOpcode(unsigned
default: llvm_unreachable("Unexpected opcode");
case ISD::FMA: Opcode = X86ISD::FNMADD; break;
case X86ISD::FMADD_RND: Opcode = X86ISD::FNMADD_RND; break;
- case X86ISD::FMADDS1: Opcode = X86ISD::FNMADDS1; break;
- case X86ISD::FMADDS3: Opcode = X86ISD::FNMADDS3; break;
- case X86ISD::FMADDS1_RND: Opcode = X86ISD::FNMADDS1_RND; break;
- case X86ISD::FMADDS3_RND: Opcode = X86ISD::FNMADDS3_RND; break;
case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break;
case X86ISD::FMSUB_RND: Opcode = X86ISD::FNMSUB_RND; break;
- case X86ISD::FMSUBS1: Opcode = X86ISD::FNMSUBS1; break;
- case X86ISD::FMSUBS3: Opcode = X86ISD::FNMSUBS3; break;
- case X86ISD::FMSUBS1_RND: Opcode = X86ISD::FNMSUBS1_RND; break;
- case X86ISD::FMSUBS3_RND: Opcode = X86ISD::FNMSUBS3_RND; break;
case X86ISD::FNMADD: Opcode = ISD::FMA; break;
case X86ISD::FNMADD_RND: Opcode = X86ISD::FMADD_RND; break;
- case X86ISD::FNMADDS1: Opcode = X86ISD::FMADDS1; break;
- case X86ISD::FNMADDS3: Opcode = X86ISD::FMADDS3; break;
- case X86ISD::FNMADDS1_RND: Opcode = X86ISD::FMADDS1_RND; break;
- case X86ISD::FNMADDS3_RND: Opcode = X86ISD::FMADDS3_RND; break;
case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break;
case X86ISD::FNMSUB_RND: Opcode = X86ISD::FMSUB_RND; break;
- case X86ISD::FNMSUBS1: Opcode = X86ISD::FMSUBS1; break;
- case X86ISD::FNMSUBS3: Opcode = X86ISD::FMSUBS3; break;
- case X86ISD::FNMSUBS1_RND: Opcode = X86ISD::FMSUBS1_RND; break;
- case X86ISD::FNMSUBS3_RND: Opcode = X86ISD::FMSUBS3_RND; break;
}
}
@@ -37737,28 +37705,12 @@ static unsigned negateFMAOpcode(unsigned
default: llvm_unreachable("Unexpected opcode");
case ISD::FMA: Opcode = X86ISD::FMSUB; break;
case X86ISD::FMADD_RND: Opcode = X86ISD::FMSUB_RND; break;
- case X86ISD::FMADDS1: Opcode = X86ISD::FMSUBS1; break;
- case X86ISD::FMADDS3: Opcode = X86ISD::FMSUBS3; break;
- case X86ISD::FMADDS1_RND: Opcode = X86ISD::FMSUBS1_RND; break;
- case X86ISD::FMADDS3_RND: Opcode = X86ISD::FMSUBS3_RND; break;
case X86ISD::FMSUB: Opcode = ISD::FMA; break;
case X86ISD::FMSUB_RND: Opcode = X86ISD::FMADD_RND; break;
- case X86ISD::FMSUBS1: Opcode = X86ISD::FMADDS1; break;
- case X86ISD::FMSUBS3: Opcode = X86ISD::FMADDS3; break;
- case X86ISD::FMSUBS1_RND: Opcode = X86ISD::FMADDS1_RND; break;
- case X86ISD::FMSUBS3_RND: Opcode = X86ISD::FMADDS3_RND; break;
case X86ISD::FNMADD: Opcode = X86ISD::FNMSUB; break;
case X86ISD::FNMADD_RND: Opcode = X86ISD::FNMSUB_RND; break;
- case X86ISD::FNMADDS1: Opcode = X86ISD::FNMSUBS1; break;
- case X86ISD::FNMADDS3: Opcode = X86ISD::FNMSUBS3; break;
- case X86ISD::FNMADDS1_RND: Opcode = X86ISD::FNMSUBS1_RND; break;
- case X86ISD::FNMADDS3_RND: Opcode = X86ISD::FNMSUBS3_RND; break;
case X86ISD::FNMSUB: Opcode = X86ISD::FNMADD; break;
case X86ISD::FNMSUB_RND: Opcode = X86ISD::FNMADD_RND; break;
- case X86ISD::FNMSUBS1: Opcode = X86ISD::FNMADDS1; break;
- case X86ISD::FNMSUBS3: Opcode = X86ISD::FNMADDS3; break;
- case X86ISD::FNMSUBS1_RND: Opcode = X86ISD::FNMADDS1_RND; break;
- case X86ISD::FNMSUBS3_RND: Opcode = X86ISD::FNMADDS3_RND; break;
}
}
@@ -37803,28 +37755,11 @@ static SDValue combineFMA(SDNode *N, Sel
return false;
};
- bool IsScalarS1 = N->getOpcode() == X86ISD::FMADDS1 ||
- N->getOpcode() == X86ISD::FMSUBS1 ||
- N->getOpcode() == X86ISD::FNMADDS1 ||
- N->getOpcode() == X86ISD::FNMSUBS1 ||
- N->getOpcode() == X86ISD::FMADDS1_RND ||
- N->getOpcode() == X86ISD::FMSUBS1_RND ||
- N->getOpcode() == X86ISD::FNMADDS1_RND ||
- N->getOpcode() == X86ISD::FNMSUBS1_RND;
- bool IsScalarS3 = N->getOpcode() == X86ISD::FMADDS3 ||
- N->getOpcode() == X86ISD::FMSUBS3 ||
- N->getOpcode() == X86ISD::FNMADDS3 ||
- N->getOpcode() == X86ISD::FNMSUBS3 ||
- N->getOpcode() == X86ISD::FMADDS3_RND ||
- N->getOpcode() == X86ISD::FMSUBS3_RND ||
- N->getOpcode() == X86ISD::FNMADDS3_RND ||
- N->getOpcode() == X86ISD::FNMSUBS3_RND;
-
// Do not convert the passthru input of scalar intrinsics.
// FIXME: We could allow negations of the lower element only.
- bool NegA = !IsScalarS1 && invertIfNegative(A);
+ bool NegA = invertIfNegative(A);
bool NegB = invertIfNegative(B);
- bool NegC = !IsScalarS3 && invertIfNegative(C);
+ bool NegC = invertIfNegative(C);
if (!NegA && !NegB && !NegC)
return SDValue();
@@ -39450,28 +39385,12 @@ SDValue X86TargetLowering::PerformDAGCom
case X86ISD::VZEXT_MOVL:
case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);
case X86ISD::FMADD_RND:
- case X86ISD::FMADDS1_RND:
- case X86ISD::FMADDS3_RND:
- case X86ISD::FMADDS1:
- case X86ISD::FMADDS3:
case X86ISD::FMSUB:
case X86ISD::FMSUB_RND:
- case X86ISD::FMSUBS1_RND:
- case X86ISD::FMSUBS3_RND:
- case X86ISD::FMSUBS1:
- case X86ISD::FMSUBS3:
case X86ISD::FNMADD:
case X86ISD::FNMADD_RND:
- case X86ISD::FNMADDS1_RND:
- case X86ISD::FNMADDS3_RND:
- case X86ISD::FNMADDS1:
- case X86ISD::FNMADDS3:
case X86ISD::FNMSUB:
case X86ISD::FNMSUB_RND:
- case X86ISD::FNMSUBS1_RND:
- case X86ISD::FNMSUBS3_RND:
- case X86ISD::FNMSUBS1:
- case X86ISD::FNMSUBS3:
case ISD::FMA: return combineFMA(N, DAG, Subtarget);
case X86ISD::FMADDSUB_RND:
case X86ISD::FMSUBADD_RND:
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=336883&r1=336882&r2=336883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jul 11 20:42:41 2018
@@ -499,19 +499,6 @@ namespace llvm {
FMADDSUB_RND,
FMSUBADD_RND,
- // Scalar intrinsic FMA.
- FMADDS1, FMADDS3,
- FNMADDS1, FNMADDS3,
- FMSUBS1, FMSUBS3,
- FNMSUBS1, FNMSUBS3,
-
- // Scalar intrinsic FMA with rounding mode.
- // Two versions, passthru bits on op1 or op3.
- FMADDS1_RND, FMADDS3_RND,
- FNMADDS1_RND, FNMADDS3_RND,
- FMSUBS1_RND, FMSUBS3_RND,
- FNMSUBS1_RND, FNMSUBS3_RND,
-
// Compress and expand.
COMPRESS,
EXPAND,
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=336883&r1=336882&r2=336883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Wed Jul 11 20:42:41 2018
@@ -6702,22 +6702,22 @@ defm VFNMSUB132 : avx512_fma3p_132_f<0
// Scalar FMA
multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
- dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
dag RHS_r, dag RHS_m, dag RHS_b, bit MaskOnlyReg> {
let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.RC:$src3), OpcodeStr,
- "$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>,
+ "$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
AVX512FMA3Base, Sched<[SchedWriteFMA.Scl]>;
+ let mayLoad = 1 in
defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
- "$src3, $src2", "$src2, $src3", RHS_VEC_m, 1, 1>,
+ "$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
AVX512FMA3Base, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>;
defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
- OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1>,
+ OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (null_frag), 1, 1>,
AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[SchedWriteFMA.Scl]>;
let isCodeGenOnly = 1, isCommutable = 1 in {
@@ -6744,18 +6744,11 @@ let Constraints = "$src1 = $dst", hasSid
multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd,
- SDNode OpNodes1, SDNode OpNodeRnds1, SDNode OpNodes3,
- SDNode OpNodeRnds3, X86VectorVTInfo _,
- string SUFF> {
+ X86VectorVTInfo _, string SUFF> {
let ExeDomain = _.ExeDomain in {
defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix, _,
// Operands for intrinsic are in 123 order to preserve passthu
// semantics.
- (_.VT (OpNodes1 _.RC:$src1, _.RC:$src2, _.RC:$src3)),
- (_.VT (OpNodes1 _.RC:$src1, _.RC:$src2,
- _.ScalarIntMemCPat:$src3)),
- (_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
- (i32 imm:$rc))),
(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
_.FRC:$src3))),
(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
@@ -6764,11 +6757,6 @@ multiclass avx512_fma3s_all<bits<8> opc2
_.FRC:$src3, (i32 imm:$rc)))), 0>;
defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix, _,
- (_.VT (OpNodes3 _.RC:$src2, _.RC:$src3, _.RC:$src1)),
- (_.VT (OpNodes3 _.RC:$src2, _.ScalarIntMemCPat:$src3,
- _.RC:$src1)),
- (_.VT ( OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
- (i32 imm:$rc))),
(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
_.FRC:$src1))),
(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
@@ -6779,10 +6767,6 @@ multiclass avx512_fma3s_all<bits<8> opc2
// One pattern is 312 order so that the load is in a different place from the
// 213 and 231 patterns this helps tablegen's duplicate pattern detection.
defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix, _,
- (null_frag),
- (_.VT (OpNodes1 _.RC:$src1, _.ScalarIntMemCPat:$src3,
- _.RC:$src2)),
- (null_frag),
(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
_.FRC:$src2))),
(set _.FRC:$dst, (_.EltVT (OpNode (_.ScalarLdFrag addr:$src3),
@@ -6793,33 +6777,21 @@ multiclass avx512_fma3s_all<bits<8> opc2
}
multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
- string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd,
- SDNode OpNodes1, SDNode OpNodeRnds1, SDNode OpNodes3,
- SDNode OpNodeRnds3> {
+ string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> {
let Predicates = [HasAVX512] in {
defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
- OpNodeRnd, OpNodes1, OpNodeRnds1, OpNodes3,
- OpNodeRnds3, f32x_info, "SS">,
+ OpNodeRnd, f32x_info, "SS">,
EVEX_CD8<32, CD8VT1>, VEX_LIG;
defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
- OpNodeRnd, OpNodes1, OpNodeRnds1, OpNodes3,
- OpNodeRnds3, f64x_info, "SD">,
+ OpNodeRnd, f64x_info, "SD">,
EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
}
}
-defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd,
- X86Fmadds1, X86FmaddRnds1, X86Fmadds3,
- X86FmaddRnds3>;
-defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd,
- X86Fmsubs1, X86FmsubRnds1, X86Fmsubs3,
- X86FmsubRnds3>;
-defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd,
- X86Fnmadds1, X86FnmaddRnds1, X86Fnmadds3,
- X86FnmaddRnds3>;
-defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd,
- X86Fnmsubs1, X86FnmsubRnds1, X86Fnmsubs3,
- X86FnmsubRnds3>;
+defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
+defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
+defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
+defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode RndOp, string Prefix,
string Suffix, SDNode Move,
Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=336883&r1=336882&r2=336883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Wed Jul 11 20:42:41 2018
@@ -304,8 +304,7 @@ multiclass fma3s_int_forms<bits<8> opc13
}
multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
- string OpStr, SDNode OpNodeIntrin, SDNode OpNode,
- X86FoldableSchedWrite sched> {
+ string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> {
let ExeDomain = SSEPackedSingle in
defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", OpNode,
FR32, f32mem, sched>,
@@ -319,14 +318,14 @@ multiclass fma3s<bits<8> opc132, bits<8>
VR128, sdmem, sched>, VEX_W;
}
-defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadds1, X86Fmadd,
+defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd,
SchedWriteFMA.Scl>, VEX_LIG;
-defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsubs1, X86Fmsub,
+defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub,
SchedWriteFMA.Scl>, VEX_LIG;
-defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadds1, X86Fnmadd,
+defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd,
SchedWriteFMA.Scl>, VEX_LIG;
-defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsubs1, X86Fnmsub,
+defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub,
SchedWriteFMA.Scl>, VEX_LIG;
multiclass scalar_fma_patterns<SDNode Op, string Prefix, string Suffix,
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=336883&r1=336882&r2=336883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Jul 11 20:42:41 2018
@@ -479,29 +479,6 @@ def X86FnmsubRnd : SDNode<"X86ISD::FN
def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>;
def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>;
-// Scalar FMA intrinsics with passthru bits in operand 1.
-def X86Fmadds1 : SDNode<"X86ISD::FMADDS1", SDTFPTernaryOp>;
-def X86Fnmadds1 : SDNode<"X86ISD::FNMADDS1", SDTFPTernaryOp>;
-def X86Fmsubs1 : SDNode<"X86ISD::FMSUBS1", SDTFPTernaryOp>;
-def X86Fnmsubs1 : SDNode<"X86ISD::FNMSUBS1", SDTFPTernaryOp>;
-
-// Scalar FMA intrinsics with passthru bits in operand 1.
-def X86FmaddRnds1 : SDNode<"X86ISD::FMADDS1_RND", SDTFmaRound>;
-def X86FnmaddRnds1 : SDNode<"X86ISD::FNMADDS1_RND", SDTFmaRound>;
-def X86FmsubRnds1 : SDNode<"X86ISD::FMSUBS1_RND", SDTFmaRound>;
-def X86FnmsubRnds1 : SDNode<"X86ISD::FNMSUBS1_RND", SDTFmaRound>;
-
-def X86Fmadds3 : SDNode<"X86ISD::FMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
-def X86Fnmadds3 : SDNode<"X86ISD::FNMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
-def X86Fmsubs3 : SDNode<"X86ISD::FMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
-def X86Fnmsubs3 : SDNode<"X86ISD::FNMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
-
-// Scalar FMA intrinsics with passthru bits in operand 3.
-def X86FmaddRnds3 : SDNode<"X86ISD::FMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
-def X86FnmaddRnds3 : SDNode<"X86ISD::FNMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
-def X86FmsubRnds3 : SDNode<"X86ISD::FMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
-def X86FnmsubRnds3 : SDNode<"X86ISD::FNMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
-
def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
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