[PATCH] D48927: [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added inline comments.


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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:3396
+                                   dag iops> {
+  def i : BaseLoadStoreUnscale<sz, 0, opc, oops, iops, asm, []>,
+          Sched<[WriteST]> {
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Could the oops and iops be set here, rather than repeating them in each instance, like we currently do for the other classes which inherit from BaseLoadStoreUnscale? You are already passing the regtype up to here, which is the only part of the operand lists which varies.


https://reviews.llvm.org/D48927