[llvm] r336712 - [X86] Remove AddedComplexity from register form of NOT. NFCI

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Jul 10 12:09:00 2018
New Revision: 336712

URL: http://llvm.org/viewvc/llvm-project?rev=336712&view=rev
Log:
[X86] Remove AddedComplexity from register form of NOT. NFCI

I believe isProfitableToFold will stop the load folding that this was intended to overcome.

Given an (xor load, -1), isProfitableToFold will see that the immediate can be folded with the xor using a one byte immediate since it can be sign extended. It doesn't know about NOT, but the one byte immediate check is enough to stop the fold.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrArithmetic.td

Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=336712&r1=336711&r2=336712&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Tue Jul 10 12:09:00 2018
@@ -391,8 +391,6 @@ def NEG64m : RI<0xF7, MRM3m, (outs), (in
 // Note: NOT does not set EFLAGS!
 
 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
-// Match xor -1 to not. Favors these over a move imm + xor to save code size.
-let AddedComplexity = 15 in {
 def NOT8r  : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
                "not{b}\t$dst",
                [(set GR8:$dst, (not GR8:$src1))]>;
@@ -404,7 +402,6 @@ def NOT32r : I<0xF7, MRM2r, (outs GR32:$
                [(set GR32:$dst, (not GR32:$src1))]>, OpSize32;
 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
                 [(set GR64:$dst, (not GR64:$src1))]>;
-}
 } // Constraints = "$src1 = $dst", SchedRW
 
 let SchedRW = [WriteALURMW] in {