[llvm] r336639 - [X86] Use IsProfitableToFold to block vinsertf128rm in favor of insert_subreg instead of artifically increasing pattern complexity to give priority.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Jul  9 23:19:54 2018
New Revision: 336639

URL: http://llvm.org/viewvc/llvm-project?rev=336639&view=rev
Log:
[X86] Use IsProfitableToFold to block vinsertf128rm in favor of insert_subreg instead of artifically increasing pattern complexity to give priority.

This is a much more direct way to solve the issue than just giving extra priority.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=336639&r1=336638&r2=336639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jul  9 23:19:54 2018
@@ -614,6 +614,11 @@ X86DAGToDAGISel::IsProfitableToFold(SDVa
     }
   }
 
+  // Prevent folding a load if this can implemented with an insert_subreg.
+  if (Root->getOpcode() == ISD::INSERT_SUBVECTOR &&
+      Root->getOperand(0).isUndef() && isNullConstant(Root->getOperand(2)))
+    return false;
+
   return true;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td?rev=336639&r1=336638&r2=336639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrVecCompiler.td Mon Jul  9 23:19:54 2018
@@ -147,7 +147,6 @@ multiclass subvector_subreg_lowering<Reg
   def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
             (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
 
-  let AddedComplexity = 25 in // to give priority over vinsertf128rm
   def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
             (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
 }