[llvm] r336531 - [AArch64][SVE] Asm: Support for UZP and TRN instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 9 02:12:17 PDT 2018
Author: s.desmalen
Date: Mon Jul 9 02:12:17 2018
New Revision: 336531
URL: http://llvm.org/viewvc/llvm-project?rev=336531&view=rev
Log:
[AArch64][SVE] Asm: Support for UZP and TRN instructions.
This patch adds support for:
UZP1 Concatenate even elements from two vectors
UZP2 Concatenate odd elements from two vectors
TRN1 Interleave even elements from two vectors
TRN2 Interleave odd elements from two vectors
With variants for both data and predicate vectors, e.g.
uzp1 z0.b, z1.b, z2.b
trn2 p0.s, p1.s, p2.s
Added:
llvm/trunk/test/MC/AArch64/SVE/trn1-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/trn1.s
llvm/trunk/test/MC/AArch64/SVE/trn2-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/trn2.s
llvm/trunk/test/MC/AArch64/SVE/uzp1-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uzp1.s
llvm/trunk/test/MC/AArch64/SVE/uzp2-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uzp2.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=336531&r1=336530&r2=336531&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Jul 9 02:12:17 2018
@@ -536,9 +536,17 @@ let Predicates = [HasSVE] in {
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
+ defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">;
+ defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">;
+ defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">;
+ defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">;
defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
+ defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">;
+ defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">;
+ defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">;
+ defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">;
def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
Added: llvm/trunk/test/MC/AArch64/SVE/trn1-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/trn1-diagnostics.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/trn1-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/trn1-diagnostics.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+trn1 z10.h, z22.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: trn1 z10.h, z22.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+trn1 z10.h, z3.h, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: trn1 z10.h, z3.h, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+trn1 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: trn1 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+trn1 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn1 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+trn1 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn1 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+trn1 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn1 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+trn1 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn1 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/trn1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/trn1.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/trn1.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/trn1.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+trn1 z31.b, z31.b, z31.b
+// CHECK-INST: trn1 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x73,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 73 3f 05 <unknown>
+
+trn1 z31.h, z31.h, z31.h
+// CHECK-INST: trn1 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x73,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 73 7f 05 <unknown>
+
+trn1 z31.s, z31.s, z31.s
+// CHECK-INST: trn1 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x73,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 73 bf 05 <unknown>
+
+trn1 z31.d, z31.d, z31.d
+// CHECK-INST: trn1 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x73,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 73 ff 05 <unknown>
+
+trn1 p15.b, p15.b, p15.b
+// CHECK-INST: trn1 p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x51,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 51 2f 05 <unknown>
+
+trn1 p15.s, p15.s, p15.s
+// CHECK-INST: trn1 p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x51,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 51 af 05 <unknown>
+
+trn1 p15.h, p15.h, p15.h
+// CHECK-INST: trn1 p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x51,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 51 6f 05 <unknown>
+
+trn1 p15.d, p15.d, p15.d
+// CHECK-INST: trn1 p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x51,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 51 ef 05 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/trn2-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/trn2-diagnostics.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/trn2-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/trn2-diagnostics.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+trn2 z6.h, z23.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: trn2 z6.h, z23.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+trn2 z0.h, z30.h, z24.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: trn2 z0.h, z30.h, z24.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+trn2 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: trn2 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+trn2 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn2 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+trn2 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn2 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+trn2 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn2 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+trn2 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: trn2 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/trn2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/trn2.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/trn2.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/trn2.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+trn2 z31.b, z31.b, z31.b
+// CHECK-INST: trn2 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x77,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 77 3f 05 <unknown>
+
+trn2 z31.h, z31.h, z31.h
+// CHECK-INST: trn2 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x77,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 77 7f 05 <unknown>
+
+trn2 z31.s, z31.s, z31.s
+// CHECK-INST: trn2 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x77,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 77 bf 05 <unknown>
+
+trn2 z31.d, z31.d, z31.d
+// CHECK-INST: trn2 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x77,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 77 ff 05 <unknown>
+
+trn2 p15.b, p15.b, p15.b
+// CHECK-INST: trn2 p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x55,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 55 2f 05 <unknown>
+
+trn2 p15.s, p15.s, p15.s
+// CHECK-INST: trn2 p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x55,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 55 af 05 <unknown>
+
+trn2 p15.h, p15.h, p15.h
+// CHECK-INST: trn2 p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x55,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 55 6f 05 <unknown>
+
+trn2 p15.d, p15.d, p15.d
+// CHECK-INST: trn2 p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x55,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 55 ef 05 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uzp1-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uzp1-diagnostics.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uzp1-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uzp1-diagnostics.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+uzp1 z10.h, z22.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: uzp1 z10.h, z22.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+uzp1 z10.h, z3.h, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzp1 z10.h, z3.h, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+uzp1 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: uzp1 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+uzp1 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp1 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+uzp1 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp1 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+uzp1 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp1 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+uzp1 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp1 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uzp1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uzp1.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uzp1.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uzp1.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uzp1 z31.b, z31.b, z31.b
+// CHECK-INST: uzp1 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x6b,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6b 3f 05 <unknown>
+
+uzp1 z31.h, z31.h, z31.h
+// CHECK-INST: uzp1 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x6b,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6b 7f 05 <unknown>
+
+uzp1 z31.s, z31.s, z31.s
+// CHECK-INST: uzp1 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x6b,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6b bf 05 <unknown>
+
+uzp1 z31.d, z31.d, z31.d
+// CHECK-INST: uzp1 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x6b,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6b ff 05 <unknown>
+
+uzp1 p15.b, p15.b, p15.b
+// CHECK-INST: uzp1 p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x49,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 49 2f 05 <unknown>
+
+uzp1 p15.s, p15.s, p15.s
+// CHECK-INST: uzp1 p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x49,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 49 af 05 <unknown>
+
+uzp1 p15.h, p15.h, p15.h
+// CHECK-INST: uzp1 p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x49,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 49 6f 05 <unknown>
+
+uzp1 p15.d, p15.d, p15.d
+// CHECK-INST: uzp1 p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x49,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 49 ef 05 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/uzp2-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uzp2-diagnostics.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uzp2-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uzp2-diagnostics.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// Invalid element kind.
+uzp2 z6.h, z23.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
+// CHECK-NEXT: uzp2 z6.h, z23.h, z31.x
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+uzp2 z0.h, z30.h, z24.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzp2 z0.h, z30.h, z24.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Too few operands
+uzp2 z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK-NEXT: uzp2 z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// z32 is not a valid SVE data register
+uzp2 z1.s, z2.s, z32.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp2 z1.s, z2.s, z32.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// p16 is not a valid SVE predicate register
+uzp2 p1.s, p2.s, p16.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp2 p1.s, p2.s, p16.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining data and predicate registers as operands
+uzp2 z1.s, z2.s, p3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp2 z1.s, z2.s, p3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Combining predicate and data registers as operands
+uzp2 p1.s, p2.s, z3.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp2 p1.s, p2.s, z3.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/uzp2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uzp2.s?rev=336531&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uzp2.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/uzp2.s Mon Jul 9 02:12:17 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uzp2 z31.b, z31.b, z31.b
+// CHECK-INST: uzp2 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x6f,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6f 3f 05 <unknown>
+
+uzp2 z31.h, z31.h, z31.h
+// CHECK-INST: uzp2 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x6f,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6f 7f 05 <unknown>
+
+uzp2 z31.s, z31.s, z31.s
+// CHECK-INST: uzp2 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x6f,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6f bf 05 <unknown>
+
+uzp2 z31.d, z31.d, z31.d
+// CHECK-INST: uzp2 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x6f,0xff,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 6f ff 05 <unknown>
+
+uzp2 p15.b, p15.b, p15.b
+// CHECK-INST: uzp2 p15.b, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x4d,0x2f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 4d 2f 05 <unknown>
+
+uzp2 p15.s, p15.s, p15.s
+// CHECK-INST: uzp2 p15.s, p15.s, p15.s
+// CHECK-ENCODING: [0xef,0x4d,0xaf,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 4d af 05 <unknown>
+
+uzp2 p15.h, p15.h, p15.h
+// CHECK-INST: uzp2 p15.h, p15.h, p15.h
+// CHECK-ENCODING: [0xef,0x4d,0x6f,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 4d 6f 05 <unknown>
+
+uzp2 p15.d, p15.d, p15.d
+// CHECK-INST: uzp2 p15.d, p15.d, p15.d
+// CHECK-ENCODING: [0xef,0x4d,0xef,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 4d ef 05 <unknown>
More information about the llvm-commits
mailing list