[llvm] r336511 - [X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 8 02:50:25 PDT 2018
Author: lebedevri
Date: Sun Jul 8 02:50:25 2018
New Revision: 336511
URL: http://llvm.org/viewvc/llvm-project?rev=336511&view=rev
Log:
[X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.
Summary:
Motivation: {F6597954}
This only does the mechanical splitting, does not actually change
any numbers, as the tests added in previous revision show.
Reviewers: craig.topper, RKSimon, courbet
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48998
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jul 8 02:50:25 2018
@@ -1371,52 +1371,52 @@ let Defs = [EFLAGS] in {
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
- PS, OpSize16, Sched<[WriteBitScan]>;
+ PS, OpSize16, Sched<[WriteBSF]>;
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>,
- PS, OpSize16, Sched<[WriteBitScanLd]>;
+ PS, OpSize16, Sched<[WriteBSFLd]>;
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>,
- PS, OpSize32, Sched<[WriteBitScan]>;
+ PS, OpSize32, Sched<[WriteBSF]>;
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>,
- PS, OpSize32, Sched<[WriteBitScanLd]>;
+ PS, OpSize32, Sched<[WriteBSFLd]>;
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>,
- PS, Sched<[WriteBitScan]>;
+ PS, Sched<[WriteBSF]>;
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>,
- PS, Sched<[WriteBitScanLd]>;
+ PS, Sched<[WriteBSFLd]>;
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>,
- PS, OpSize16, Sched<[WriteBitScan]>;
+ PS, OpSize16, Sched<[WriteBSR]>;
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>,
- PS, OpSize16, Sched<[WriteBitScanLd]>;
+ PS, OpSize16, Sched<[WriteBSRLd]>;
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>,
- PS, OpSize32, Sched<[WriteBitScan]>;
+ PS, OpSize32, Sched<[WriteBSR]>;
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>,
- PS, OpSize32, Sched<[WriteBitScanLd]>;
+ PS, OpSize32, Sched<[WriteBSRLd]>;
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>,
- PS, Sched<[WriteBitScan]>;
+ PS, Sched<[WriteBSR]>;
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>,
- PS, Sched<[WriteBitScanLd]>;
+ PS, Sched<[WriteBSRLd]>;
} // Defs = [EFLAGS]
let SchedRW = [WriteMicrocoded] in {
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Jul 8 02:50:25 2018
@@ -137,10 +137,11 @@ def : WriteRes<WriteSETCCStore, [BWPort
def : WriteRes<WriteLAHFSAHF, [BWPort06]>;
// Bit counts.
-defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
-defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
-defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
-defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
+defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
+defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
+defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
+defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
+defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
// Integer shifts and rotates.
defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Jul 8 02:50:25 2018
@@ -143,10 +143,11 @@ def : WriteRes<WriteLAHFSAHF, [HWPort06
def : WriteRes<WriteLEA, [HWPort15]>;
// Bit counts.
-defm : HWWriteResPair<WriteBitScan, [HWPort1], 3>;
-defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>;
-defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>;
-defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>;
+defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;
+defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;
+defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>;
+defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>;
+defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>;
// BMI1 BEXTR, BMI2 BZHI
defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Jul 8 02:50:25 2018
@@ -142,10 +142,11 @@ def : WriteRes<WriteLAHFSAHF, [SBPort05
def : WriteRes<WriteLEA, [SBPort01]>;
// Bit counts.
-defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
-defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>;
-defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>;
-defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>;
+defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>;
// BMI1 BEXTR, BMI2 BZHI
// NOTE: These don't exist on Sandy Bridge. Ports are guesses.
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Jul 8 02:50:25 2018
@@ -135,10 +135,11 @@ def : WriteRes<WriteSETCCStore, [SKLPor
def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
// Bit counts.
-defm : SKLWriteResPair<WriteBitScan, [SKLPort1], 3>;
-defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>;
-defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>;
-defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;
+defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
+defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
+defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>;
+defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>;
+defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>;
// Integer shifts and rotates.
defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Jul 8 02:50:25 2018
@@ -138,10 +138,11 @@ def : WriteRes<WriteLAHFSAHF, [SKXPort0
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
// Bit counts.
-defm : SKXWriteResPair<WriteBitScan, [SKXPort1], 3>;
-defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
-defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
-defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
+defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
+defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
+defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
+defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
+defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
// BMI1 BEXTR, BMI2 BZHI
defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Sun Jul 8 02:50:25 2018
@@ -128,7 +128,8 @@ defm WriteIDiv16 : X86SchedWritePair;
defm WriteIDiv32 : X86SchedWritePair;
defm WriteIDiv64 : X86SchedWritePair;
-defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse.
+defm WriteBSF : X86SchedWritePair; // Bit scan forward.
+defm WriteBSR : X86SchedWritePair; // Bit scan reverse.
defm WritePOPCNT : X86SchedWritePair; // Bit population count.
defm WriteLZCNT : X86SchedWritePair; // Leading zero count.
defm WriteTZCNT : X86SchedWritePair; // Trailing zero count.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Sun Jul 8 02:50:25 2018
@@ -131,7 +131,8 @@ def : InstRW<[AtomWriteIMul64I], (instrs
IMUL64rmi8, IMUL64rmi32)>;
// Bit counts.
-defm : AtomWriteResPair<WriteBitScan, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
+defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
+defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
defm : X86WriteResPairUnsupported<WritePOPCNT>;
defm : X86WriteResPairUnsupported<WriteLZCNT>;
defm : X86WriteResPairUnsupported<WriteTZCNT>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Sun Jul 8 02:50:25 2018
@@ -184,10 +184,11 @@ def : WriteRes<WriteLAHFSAHF, [JALU01]>
def : WriteRes<WriteLEA, [JALU01]>;
// Bit counts.
-defm : JWriteResIntPair<WriteBitScan, [JALU01], 5, [4], 8>;
-defm : JWriteResIntPair<WritePOPCNT, [JALU01], 1>;
-defm : JWriteResIntPair<WriteLZCNT, [JALU01], 1>;
-defm : JWriteResIntPair<WriteTZCNT, [JALU01], 2, [2]>;
+defm : JWriteResIntPair<WriteBSF, [JALU01], 5, [4], 8>;
+defm : JWriteResIntPair<WriteBSR, [JALU01], 5, [4], 8>;
+defm : JWriteResIntPair<WritePOPCNT, [JALU01], 1>;
+defm : JWriteResIntPair<WriteLZCNT, [JALU01], 1>;
+defm : JWriteResIntPair<WriteTZCNT, [JALU01], 2, [2]>;
// BMI1 BEXTR, BMI2 BZHI
defm : JWriteResIntPair<WriteBEXTR, [JALU01], 1>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sun Jul 8 02:50:25 2018
@@ -117,10 +117,11 @@ def : WriteRes<WriteLAHFSAHF, [SLM_IEC_
def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
// Bit counts.
-defm : SLMWriteResPair<WriteBitScan, [SLM_IEC_RSV01], 10, [20], 10>;
-defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;
-defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;
-defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;
+defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>;
+defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>;
+defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;
+defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;
+defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;
// BMI1 BEXTR, BMI2 BZHI
defm : X86WriteResPairUnsupported<WriteBEXTR>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=336511&r1=336510&r2=336511&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sun Jul 8 02:50:25 2018
@@ -190,10 +190,11 @@ def : WriteRes<WriteSETCCStore, [ZnALU
defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>;
// Bit counts.
-defm : ZnWriteResPair<WriteBitScan, [ZnALU], 3>;
-defm : ZnWriteResPair<WriteLZCNT, [ZnALU], 2>;
-defm : ZnWriteResPair<WriteTZCNT, [ZnALU], 2>;
-defm : ZnWriteResPair<WritePOPCNT, [ZnALU], 1>;
+defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>;
+defm : ZnWriteResPair<WriteBSR, [ZnALU], 3>;
+defm : ZnWriteResPair<WriteLZCNT, [ZnALU], 2>;
+defm : ZnWriteResPair<WriteTZCNT, [ZnALU], 2>;
+defm : ZnWriteResPair<WritePOPCNT, [ZnALU], 1>;
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
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