[PATCH] D49015: [X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble class

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86Schedule.td:145
+// Double shift instructions.
+defm WriteShiftDouble : X86SchedWritePair;
 
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I'm not sure a basic sched pair is the best match for double shifts, at least on AMD targets the imm/reg versions and the RMW versions are all pretty different in their behaviours - see X86ScheduleBtVer2.td.

I'd be a lot happier if we had better perf numbers for all of these (we did some for Jaguar but nothing else - we need some decent Intel tests for starters) and then we can decide how to create the classes to match.

@lebedev.ri What do you think?


Repository:
  rL LLVM

https://reviews.llvm.org/D49015