[PATCH] D49029: [AMDGPU] Use new hasDummyOperands on vop3_real

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, t-tye, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

This ensures that the MC decoder leaves a dummy operand for the missing
src2 modifiers on a mac, without the hack to insert it manually.

This change requires https://reviews.llvm.org/D49027.

Change-Id: I18681ee99da9c5b9650ee05d5d305a8e5d0dfe09


Repository:
  rL LLVM

https://reviews.llvm.org/D49029

Files:
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/VOPInstructions.td


Index: lib/Target/AMDGPU/VOPInstructions.td
===================================================================
--- lib/Target/AMDGPU/VOPInstructions.td
+++ lib/Target/AMDGPU/VOPInstructions.td
@@ -143,6 +143,8 @@
   let isPseudo = 0;
   let isCodeGenOnly = 0;
   let UseNamedOperandTable = 1;
+  // Leave a gap when decoding a vop3 mac for the missing src2 modifiers.
+  let hasDummyOperands = 1;
 
   let Constraints     = ps.Constraints;
   let DisableEncoding = ps.DisableEncoding;
Index: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
===================================================================
--- lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -243,15 +243,6 @@
     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
   } while (false);
 
-  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
-              MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
-              MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
-              MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi)) {
-    // Insert dummy unused src2_modifiers.
-    insertNamedMCOperand(MI, MCOperand::createImm(0),
-                         AMDGPU::OpName::src2_modifiers);
-  }
-
   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
     Res = convertMIMGInst(MI);
   }


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