[PATCH] D49027: [TableGen] FixedLenDecoderEmitter: allow for dummy operand in MCInst

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added a subscriber: llvm-commits.

Normally a "dummy" operand, one named in InOperandList or OutOperandList
but with no bits in the instruction encoding, is not included in an
MCInst, and the autogenerated decoding code for the disassembler
generated by FixedLenDecodeEmitter reflects that: for any such dummy
operand, no MCOperand is pushed onto the MCInst.

I have a case where it would help commoning up of essentially the same
instruction between different variants of the cpu to have a dummy
operand represented in the MCInst.

Thus I have added a new field in an instruction "hasDummyOperands".
Normally 0, when set to 1 it causes the disassembler to push an
immediate zero MCOperand for any dummy operand.

There is no test for this, but a future AMDGPU commit will use it and
thus exercise it in its tests.

Change-Id: I82b7e1f75b466f24889434c1733c6dd78ec91dbd


Repository:
  rL LLVM

https://reviews.llvm.org/D49027

Files:
  include/llvm/Target/Target.td
  utils/TableGen/FixedLenDecoderEmitter.cpp


Index: utils/TableGen/FixedLenDecoderEmitter.cpp
===================================================================
--- utils/TableGen/FixedLenDecoderEmitter.cpp
+++ utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -2016,7 +2016,9 @@
     if (Base != ~0U)
       OpInfo.addField(Base, Width, Offset);
 
-    if (OpInfo.numFields() > 0)
+    // For an operand with no bits in the instruction encoding, push it only if
+    // hasDummyOperands is true.
+    if (OpInfo.numFields() > 0 || Def.getValueAsBit("hasDummyOperands"))
       InsnOperands.push_back(OpInfo);
   }
 
Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -580,6 +580,12 @@
   /// instruction selection predicates. FastISel cannot handle such cases, but
   /// SelectionDAG can.
   bit FastISelShouldIgnore = 0;
+
+  /// Normally a "dummy" operand (an operand named in InOperandList or
+  /// OutOperandList but not appearing in the instruction encoding) does not
+  /// appear in the MCInst. Setting this to 1 means that the disassembler
+  /// pushes an immediate 0 operand onto the MCInst for such a dummy operand.
+  bit hasDummyOperands = 0;
 }
 
 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.


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