[PATCH] D49004: [CodeGen] Emit more precise AssertZext/AssertSext nodes.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/frame-index-elimination.ll:143
 ; CI: v_add_i32_e32 v0, vcc, 4, [[ADD]]
-; CI: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}}
+; CI: buffer_load_dword v1, v1, s[0:3], s4 offen offset:4{{$}}
 
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This probably makes sense. We can't use the constant offset addressing mode if we don't know if the base address is >= 0


Repository:
  rL LLVM

https://reviews.llvm.org/D49004