[PATCH] D49007: [PowerPC] Add a peephole post RA to transform the inst that fed by add

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: hfinkel, nemanjai.
Herald added subscribers: kbarton, hiraditya.

If the arch is https://reviews.llvm.org/P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e.
y = add imm, reg
LFDX. 0, y
-->
LFD imm(reg)


https://reviews.llvm.org/D49007

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
  llvm/test/CodeGen/PowerPC/branch_coalesce.ll
  llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
  llvm/test/CodeGen/PowerPC/float-to-int.ll
  llvm/test/CodeGen/PowerPC/fmf-propagation.ll
  llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
  llvm/test/CodeGen/PowerPC/i64-to-float.ll
  llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll
  llvm/test/CodeGen/PowerPC/mcm-12.ll
  llvm/test/CodeGen/PowerPC/mcm-4.ll
  llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
  llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll
  llvm/test/CodeGen/PowerPC/pr25157-peephole.ll
  llvm/test/CodeGen/PowerPC/pr25157.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/PowerPC/toc-float.ll
  llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

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