[llvm] r336400 - [X86][Disassembler] Fix LOCK prefix disassembler support
Maksim Panchenko via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 5 16:32:42 PDT 2018
Author: maks
Date: Thu Jul 5 16:32:42 2018
New Revision: 336400
URL: http://llvm.org/viewvc/llvm-project?rev=336400&view=rev
Log:
[X86][Disassembler] Fix LOCK prefix disassembler support
Summary:
If LOCK prefix is not the first prefix in an instruction, LLVM
disassembler silently drops the prefix.
The fix is to select a proper instruction with a builtin LOCK prefix if
one exists.
Reviewers: craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49001
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
llvm/trunk/test/MC/Disassembler/X86/prefixes.txt
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=336400&r1=336399&r2=336400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Thu Jul 5 16:32:42 2018
@@ -247,6 +247,8 @@ MCDisassembler::DecodeStatus X86GenericD
// It should not be 'pause' f3 90
InternalInstr.opcode != 0x90)
Flags |= X86::IP_HAS_REPEAT;
+ if (InternalInstr.hasLockPrefix)
+ Flags |= X86::IP_HAS_LOCK;
}
Instr.setFlags(Flags);
}
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=336400&r1=336399&r2=336400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu Jul 5 16:32:42 2018
@@ -298,6 +298,9 @@ static bool isREX(struct InternalInstruc
static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) {
uint8_t nextByte;
switch (prefix) {
+ case 0xf0:
+ insn->hasLockPrefix = true;
+ break;
case 0xf2:
case 0xf3:
if (lookAtByte(insn, &nextByte))
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h?rev=336400&r1=336399&r2=336400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h Thu Jul 5 16:32:42 2018
@@ -563,6 +563,8 @@ struct InternalInstruction {
bool hasAdSize;
// Operand-size override
bool hasOpSize;
+ // Lock prefix
+ bool hasLockPrefix;
// The repeat prefix if any
uint8_t repeatPrefix;
Modified: llvm/trunk/test/MC/Disassembler/X86/prefixes.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/prefixes.txt?rev=336400&r1=336399&r2=336400&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/prefixes.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/prefixes.txt Thu Jul 5 16:32:42 2018
@@ -101,6 +101,10 @@
# CHECK: movq %mm0, %mm1
0x46 0x0f 0x7f 0xc1
+# Test that lock prefix is not dropped if it's not the first prefix
+# CHECK: lock cmpxchgw %di, (%rcx)
+0x66 0xf0 0x0f 0xb1 0x39
+
# Test that a prefix on it's own works. It's debatable as to if this is
# something that is considered valid, but however as LLVM's own disassembler
# has decided to disassemble prefixes as being separate opcodes, it therefore
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