[llvm] r336295 - [PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 4 11:54:25 PDT 2018
Author: stefanp
Date: Wed Jul 4 11:54:25 2018
New Revision: 336295
URL: http://llvm.org/viewvc/llvm-project?rev=336295&view=rev
Log:
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler
We want to run the Machine Scheduler instead of the List Scheduler after RA.
Checked with a performance run on a Power 9 machine with SPEC 2006 and while
some benchmarks improved and others degraded the geomean was slightly improved
with the Machine Scheduler.
Differential Revision: https://reviews.llvm.org/D45265
Modified:
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/trunk/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
llvm/trunk/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll
llvm/trunk/test/CodeGen/PowerPC/MergeConsecutiveStores.ll
llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll
llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll
llvm/trunk/test/CodeGen/PowerPC/coldcc.ll
llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll
llvm/trunk/test/CodeGen/PowerPC/fabs.ll
llvm/trunk/test/CodeGen/PowerPC/fmf-propagation.ll
llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
llvm/trunk/test/CodeGen/PowerPC/fsub-fneg.ll
llvm/trunk/test/CodeGen/PowerPC/i1-ext-fold.ll
llvm/trunk/test/CodeGen/PowerPC/i1-to-double.ll
llvm/trunk/test/CodeGen/PowerPC/i64_fp_round.ll
llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll
llvm/trunk/test/CodeGen/PowerPC/machine-combiner.ll
llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
llvm/trunk/test/CodeGen/PowerPC/p8-isel-sched.ll
llvm/trunk/test/CodeGen/PowerPC/peephole-align.ll
llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll
llvm/trunk/test/CodeGen/PowerPC/pr27078.ll
llvm/trunk/test/CodeGen/PowerPC/pr33093.ll
llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll
llvm/trunk/test/CodeGen/PowerPC/qpx-recipest.ll
llvm/trunk/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll
llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
llvm/trunk/test/CodeGen/PowerPC/select_const.ll
llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll
llvm/trunk/test/CodeGen/PowerPC/shift128.ll
llvm/trunk/test/CodeGen/PowerPC/store-constant.ll
llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll
llvm/trunk/test/CodeGen/PowerPC/testBitReverse.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll
llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll
llvm/trunk/test/CodeGen/PowerPC/unal-vec-ldst.ll
llvm/trunk/test/CodeGen/PowerPC/vselect-constants.ll
llvm/trunk/test/CodeGen/PowerPC/vsx.ll
llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Jul 4 11:54:25 2018
@@ -24,6 +24,7 @@
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
@@ -303,7 +304,12 @@ namespace {
class PPCPassConfig : public TargetPassConfig {
public:
PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
- : TargetPassConfig(TM, PM) {}
+ : TargetPassConfig(TM, PM) {
+ // At any optimization level above -O0 we use the Machine Scheduler and not
+ // the default Post RA List Scheduler.
+ if (TM.getOptLevel() != CodeGenOpt::None)
+ substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
+ }
PPCTargetMachine &getPPCTargetMachine() const {
return getTM<PPCTargetMachine>();
Modified: llvm/trunk/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll Wed Jul 4 11:54:25 2018
@@ -15,8 +15,8 @@ define i32 @test(i32 %i) {
; CHECK-NEXT: lbzx 3, 4, 3
; CHECK-NEXT: ld 4, .LC1 at toc@l(5)
; CHECK-NEXT: subfic 3, 3, 1
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: ld 4, 0(4)
+; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: sldi 3, 3, 2
; CHECK-NEXT: lwzx 3, 4, 3
; CHECK-NEXT: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll Wed Jul 4 11:54:25 2018
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
@@ -8,26 +9,25 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: stwu 1, -464(1)
; CHECK-NEXT: lis 3, .LCPI0_0 at ha
; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: lfs 27, .LCPI0_0 at l(3)
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
-; CHECK-NEXT: lfs 27, .LCPI0_0 at l(3)
-; CHECK-NEXT: mfcr 12
; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
+; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: stw 12, 408(1)
+; CHECK-NEXT: fcmpu 1, 1, 27
; CHECK-NEXT: stfd 2, 376(1)
+; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: stfd 1, 384(1)
-; CHECK-NEXT: nop
-; CHECK-NEXT: fcmpu 0, 2, 27
+; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: lwz 3, 380(1)
; CHECK-NEXT: lwz 4, 376(1)
; CHECK-NEXT: lwz 5, 388(1)
; CHECK-NEXT: lwz 6, 384(1)
-; CHECK-NEXT: fcmpu 1, 1, 27
-; CHECK-NEXT: crand 20, 6, 0
-; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: stw 3, 396(1)
; CHECK-NEXT: stw 4, 392(1)
; CHECK-NEXT: stw 5, 404(1)
@@ -44,8 +44,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: lis 3, 15856
; CHECK-NEXT: stfd 1, 304(1)
; CHECK-NEXT: stfd 0, 296(1)
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
; CHECK-NEXT: lwz 4, 308(1)
; CHECK-NEXT: lwz 5, 304(1)
; CHECK-NEXT: lwz 6, 300(1)
@@ -58,7 +56,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: stw 5, 320(1)
; CHECK-NEXT: stw 6, 316(1)
; CHECK-NEXT: stw 7, 312(1)
-; CHECK-NEXT: nop
; CHECK-NEXT: lfd 31, 320(1)
; CHECK-NEXT: lfd 30, 312(1)
; CHECK-NEXT: lfd 3, 336(1)
@@ -67,31 +64,31 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: fmr 2, 30
; CHECK-NEXT: bl __gcc_qmul at PLT
; CHECK-NEXT: stfd 1, 280(1)
-; CHECK-NEXT: stfd 2, 288(1)
; CHECK-NEXT: lis 3, .LCPI0_1 at ha
-; CHECK-NEXT: fmr 29, 1
-; CHECK-NEXT: fmr 28, 2
-; CHECK-NEXT: fcmpu 0, 2, 27
+; CHECK-NEXT: stfd 2, 288(1)
+; CHECK-NEXT: lfs 0, .LCPI0_1 at l(3)
+; CHECK-NEXT: lis 3, 16864
; CHECK-NEXT: lwz 4, 284(1)
; CHECK-NEXT: lwz 5, 280(1)
; CHECK-NEXT: lwz 6, 292(1)
; CHECK-NEXT: lwz 7, 288(1)
-; CHECK-NEXT: lfs 0, .LCPI0_1 at l(3)
-; CHECK-NEXT: lis 3, 16864
+; CHECK-NEXT: fmr 29, 1
; CHECK-NEXT: stw 29, 372(1)
; CHECK-NEXT: stw 3, 368(1)
+; CHECK-NEXT: fmr 28, 2
; CHECK-NEXT: stw 29, 364(1)
; CHECK-NEXT: stw 29, 360(1)
+; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: stw 4, 356(1)
; CHECK-NEXT: stw 5, 352(1)
+; CHECK-NEXT: fcmpu 1, 1, 0
; CHECK-NEXT: stw 6, 348(1)
; CHECK-NEXT: stw 7, 344(1)
-; CHECK-NEXT: fcmpu 1, 1, 0
+; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: lfd 3, 368(1)
; CHECK-NEXT: lfd 4, 360(1)
; CHECK-NEXT: lfd 1, 352(1)
; CHECK-NEXT: lfd 2, 344(1)
-; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: cror 8, 5, 20
; CHECK-NEXT: bl __gcc_qsub at PLT
; CHECK-NEXT: mffs 0
@@ -108,7 +105,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: fctiwz 1, 2
; CHECK-NEXT: stfd 0, 160(1)
; CHECK-NEXT: stfd 1, 152(1)
-; CHECK-NEXT: nop
; CHECK-NEXT: lwz 3, 164(1)
; CHECK-NEXT: lwz 4, 156(1)
; CHECK-NEXT: addis 3, 3, -32768
@@ -119,28 +115,27 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: .LBB0_4: # %bb1
; CHECK-NEXT: addi 30, 3, 0
; CHECK-NEXT: .LBB0_5: # %bb1
-; CHECK-NEXT: mr 3, 30
; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: mr 3, 30
; CHECK-NEXT: bl __floatditf at PLT
; CHECK-NEXT: stfd 1, 208(1)
-; CHECK-NEXT: stfd 2, 200(1)
; CHECK-NEXT: lis 3, 17392
+; CHECK-NEXT: stfd 2, 200(1)
; CHECK-NEXT: fmr 28, 1
-; CHECK-NEXT: fmr 29, 2
-; CHECK-NEXT: cmpwi 2, 30, 0
; CHECK-NEXT: lwz 4, 212(1)
; CHECK-NEXT: lwz 5, 208(1)
; CHECK-NEXT: lwz 6, 204(1)
; CHECK-NEXT: lwz 7, 200(1)
+; CHECK-NEXT: fmr 29, 2
; CHECK-NEXT: stw 29, 244(1)
; CHECK-NEXT: stw 3, 240(1)
+; CHECK-NEXT: cmpwi 2, 30, 0
; CHECK-NEXT: stw 29, 236(1)
; CHECK-NEXT: stw 29, 232(1)
; CHECK-NEXT: stw 4, 228(1)
; CHECK-NEXT: stw 5, 224(1)
; CHECK-NEXT: stw 6, 220(1)
; CHECK-NEXT: stw 7, 216(1)
-; CHECK-NEXT: nop
; CHECK-NEXT: lfd 3, 240(1)
; CHECK-NEXT: lfd 4, 232(1)
; CHECK-NEXT: lfd 1, 224(1)
@@ -157,13 +152,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: .LBB0_9: # %bb1
; CHECK-NEXT: stfd 2, 192(1)
; CHECK-NEXT: fmr 1, 31
-; CHECK-NEXT: fmr 2, 30
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
; CHECK-NEXT: lwz 3, 188(1)
; CHECK-NEXT: lwz 4, 184(1)
; CHECK-NEXT: lwz 5, 196(1)
; CHECK-NEXT: lwz 6, 192(1)
+; CHECK-NEXT: fmr 2, 30
; CHECK-NEXT: stw 3, 260(1)
; CHECK-NEXT: stw 4, 256(1)
; CHECK-NEXT: stw 5, 252(1)
@@ -172,31 +165,30 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: lfd 4, 248(1)
; CHECK-NEXT: bl __gcc_qsub at PLT
; CHECK-NEXT: stfd 2, 176(1)
+; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: stfd 1, 168(1)
; CHECK-NEXT: fcmpu 1, 1, 27
-; CHECK-NEXT: fcmpu 0, 2, 27
; CHECK-NEXT: lwz 3, 180(1)
; CHECK-NEXT: lwz 4, 176(1)
; CHECK-NEXT: lwz 5, 172(1)
; CHECK-NEXT: lwz 6, 168(1)
; CHECK-NEXT: crandc 20, 6, 0
-; CHECK-NEXT: cror 21, 5, 7
-; CHECK-NEXT: cror 20, 21, 20
; CHECK-NEXT: stw 3, 268(1)
; CHECK-NEXT: stw 4, 264(1)
+; CHECK-NEXT: cror 21, 5, 7
; CHECK-NEXT: stw 5, 276(1)
; CHECK-NEXT: stw 6, 272(1)
+; CHECK-NEXT: cror 20, 21, 20
; CHECK-NEXT: lfd 30, 264(1)
; CHECK-NEXT: lfd 31, 272(1)
; CHECK-NEXT: bc 12, 20, .LBB0_13
; CHECK-NEXT: # %bb.10: # %bb2
; CHECK-NEXT: fneg 29, 31
; CHECK-NEXT: fneg 28, 30
-; CHECK-NEXT: li 29, 0
-; CHECK-NEXT: lis 3, 16864
; CHECK-NEXT: stfd 29, 48(1)
+; CHECK-NEXT: li 29, 0
; CHECK-NEXT: stfd 28, 40(1)
-; CHECK-NEXT: nop
+; CHECK-NEXT: lis 3, 16864
; CHECK-NEXT: lwz 4, 52(1)
; CHECK-NEXT: lwz 5, 48(1)
; CHECK-NEXT: lwz 6, 44(1)
@@ -209,35 +201,33 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: stw 5, 64(1)
; CHECK-NEXT: stw 6, 60(1)
; CHECK-NEXT: stw 7, 56(1)
-; CHECK-NEXT: nop
; CHECK-NEXT: lfd 3, 80(1)
; CHECK-NEXT: lfd 4, 72(1)
; CHECK-NEXT: lfd 1, 64(1)
; CHECK-NEXT: lfd 2, 56(1)
; CHECK-NEXT: bl __gcc_qsub at PLT
; CHECK-NEXT: lis 3, .LCPI0_2 at ha
-; CHECK-NEXT: lis 4, .LCPI0_3 at ha
; CHECK-NEXT: lfs 0, .LCPI0_2 at l(3)
-; CHECK-NEXT: mffs 11
-; CHECK-NEXT: mtfsb1 31
+; CHECK-NEXT: lis 4, .LCPI0_3 at ha
; CHECK-NEXT: lfs 3, .LCPI0_3 at l(4)
-; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: fcmpu 0, 30, 0
+; CHECK-NEXT: mffs 0
+; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: fcmpu 1, 31, 3
-; CHECK-NEXT: fadd 1, 2, 1
; CHECK-NEXT: crandc 20, 6, 1
-; CHECK-NEXT: mtfsf 1, 11
+; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: cror 20, 4, 20
+; CHECK-NEXT: fadd 1, 2, 1
+; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: mtfsb0 30
-; CHECK-NEXT: fadd 12, 28, 29
+; CHECK-NEXT: fadd 2, 28, 29
; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: fctiwz 0, 1
-; CHECK-NEXT: fctiwz 13, 12
+; CHECK-NEXT: fctiwz 1, 2
; CHECK-NEXT: stfd 0, 32(1)
-; CHECK-NEXT: stfd 13, 24(1)
-; CHECK-NEXT: nop
+; CHECK-NEXT: stfd 1, 24(1)
; CHECK-NEXT: lwz 3, 36(1)
; CHECK-NEXT: lwz 4, 28(1)
; CHECK-NEXT: addis 3, 3, -32768
@@ -251,8 +241,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: b .LBB0_16
; CHECK-NEXT: .LBB0_13: # %bb3
; CHECK-NEXT: stfd 31, 112(1)
-; CHECK-NEXT: stfd 30, 104(1)
; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: stfd 30, 104(1)
; CHECK-NEXT: lis 4, 16864
; CHECK-NEXT: lwz 5, 116(1)
; CHECK-NEXT: lwz 6, 112(1)
@@ -266,35 +256,33 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: stw 6, 128(1)
; CHECK-NEXT: stw 7, 124(1)
; CHECK-NEXT: stw 8, 120(1)
-; CHECK-NEXT: nop
; CHECK-NEXT: lfd 3, 144(1)
; CHECK-NEXT: lfd 4, 136(1)
; CHECK-NEXT: lfd 1, 128(1)
; CHECK-NEXT: lfd 2, 120(1)
; CHECK-NEXT: bl __gcc_qsub at PLT
; CHECK-NEXT: lis 3, .LCPI0_0 at ha
-; CHECK-NEXT: lis 4, .LCPI0_1 at ha
; CHECK-NEXT: lfs 0, .LCPI0_0 at l(3)
-; CHECK-NEXT: mffs 11
-; CHECK-NEXT: mtfsb1 31
+; CHECK-NEXT: lis 4, .LCPI0_1 at ha
; CHECK-NEXT: lfs 3, .LCPI0_1 at l(4)
-; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: fcmpu 0, 30, 0
+; CHECK-NEXT: mffs 0
+; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: fcmpu 1, 31, 3
-; CHECK-NEXT: fadd 1, 2, 1
; CHECK-NEXT: crandc 20, 6, 0
-; CHECK-NEXT: mtfsf 1, 11
+; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: cror 20, 5, 20
+; CHECK-NEXT: fadd 1, 2, 1
+; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: mtfsb0 30
-; CHECK-NEXT: fadd 12, 30, 31
+; CHECK-NEXT: fadd 2, 30, 31
; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: fctiwz 0, 1
-; CHECK-NEXT: fctiwz 13, 12
+; CHECK-NEXT: fctiwz 1, 2
; CHECK-NEXT: stfd 0, 96(1)
-; CHECK-NEXT: stfd 13, 88(1)
-; CHECK-NEXT: nop
+; CHECK-NEXT: stfd 1, 88(1)
; CHECK-NEXT: lwz 3, 100(1)
; CHECK-NEXT: lwz 4, 92(1)
; CHECK-NEXT: addis 3, 3, -32768
@@ -308,13 +296,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) n
; CHECK-NEXT: lwz 12, 408(1)
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload
; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload
; CHECK-NEXT: lwz 0, 468(1)
-; CHECK-NEXT: mtcrf 32, 12 # cr2
; CHECK-NEXT: addi 1, 1, 464
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2016-04-28-setjmp.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2016-04-28-setjmp.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2016-04-28-setjmp.ll Wed Jul 4 11:54:25 2018
@@ -8,7 +8,7 @@ target triple = "powerpc64le-unknown-lin
; EH_SjLj_Setup.
; CHECK: li 3, 1
-; CHECK-NEXT: cmplwi 3, 0
+; CHECK: cmplwi 3, 0
define void @h() nounwind {
%1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8
Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/Frames-large.ll Wed Jul 4 11:54:25 2018
@@ -20,8 +20,8 @@ define i32* @f1() nounwind {
; PPC32-FP: _f1:
; PPC32-FP: lis r0, -1
-; PPC32-FP: stw r31, -4(r1)
; PPC32-FP: ori r0, r0, 32736
+; PPC32-FP: stw r31, -4(r1)
; PPC32-FP: stwux r1, r1, r0
; PPC32-FP: mr r31, r1
; PPC32-FP: addi r3, r31, 32
@@ -41,8 +41,8 @@ define i32* @f1() nounwind {
; PPC64-FP: _f1:
; PPC64-FP: lis r0, -1
-; PPC64-FP: std r31, -8(r1)
; PPC64-FP: ori r0, r0, 32704
+; PPC64-FP: std r31, -8(r1)
; PPC64-FP: stdux r1, r1, r0
; PPC64-FP: mr r31, r1
; PPC64-FP: addi r3, r31, 60
Modified: llvm/trunk/test/CodeGen/PowerPC/MergeConsecutiveStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/MergeConsecutiveStores.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/MergeConsecutiveStores.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/MergeConsecutiveStores.ll Wed Jul 4 11:54:25 2018
@@ -24,10 +24,10 @@
;; CHECK-LABEL: f:
;; CHECK: lwzu
+;; CHECK: stwu
;; CHECK-NEXT: lwz
;; CHECK-NEXT: lwz
;; CHECK-NEXT: lwz
-;; CHECK-NEXT: stwu
;; CHECK-NEXT: stw
;; CHECK-NEXT: stw
;; CHECK-NEXT: stw
Modified: llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll Wed Jul 4 11:54:25 2018
@@ -11,10 +11,10 @@
define signext i32 @main() {
; CHECK-LABEL: main:
; CHECK: li 3, -32477
-; CHECK: lis 12, 0
; CHECK: li 6, 234
; CHECK: sth 3, 46(1)
-; CHECK: ori 4, 12, 33059
+; CHECK: lis 3, 0
+; CHECK: ori 4, 3, 33059
; CHECK: sync
; CHECK: .LBB0_1: # %L.entry
; CHECK: lharx 3, 0, 5
@@ -32,20 +32,20 @@ define signext i32 @main() {
; CHECK: cmplwi 3, 234
;
; CHECK-P7-LABEL: main:
+; CHECK-P7: li 3, -32477
; CHECK-P7: lis 4, 0
; CHECK-P7: li 7, 0
-; CHECK-P7: li 3, -32477
-; CHECK-P7: sth 3, 46(1)
; CHECK-P7: li 5, 234
+; CHECK-P7: sth 3, 46(1)
; CHECK-P7: ori 4, 4, 33059
; CHECK-P7: rlwinm 3, 6, 3, 27, 27
; CHECK-P7: ori 7, 7, 65535
; CHECK-P7: sync
; CHECK-P7: slw 8, 5, 3
-; CHECK-P7: slw 5, 7, 3
; CHECK-P7: slw 9, 4, 3
-; CHECK-P7: and 7, 8, 5
; CHECK-P7: rldicr 4, 6, 0, 61
+; CHECK-P7: slw 5, 7, 3
+; CHECK-P7: and 7, 8, 5
; CHECK-P7: and 8, 9, 5
; CHECK-P7: .LBB0_1: # %L.entry
; CHECK-P7: lwarx 9, 0, 4
Modified: llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addi-offset-fold.ll Wed Jul 4 11:54:25 2018
@@ -27,7 +27,6 @@ entry:
; FIXME: We don't need to do these stores/loads at all.
; CHECK-DAG: std 3, -24(1)
; CHECK-DAG: stb 4, -16(1)
-; CHECK: ori 2, 2, 0
; CHECK-DAG: lbz [[REG1:[0-9]+]], -16(1)
; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG1]], 32
Modified: llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll Wed Jul 4 11:54:25 2018
@@ -35,7 +35,6 @@ define i8 @test3(i8* %ptr) {
; PPC64LE-LABEL: test3:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
-; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
@@ -79,7 +78,6 @@ define i16 @test7(i16* %ptr) {
; PPC64LE-LABEL: test7:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
-; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lhz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
@@ -123,7 +121,6 @@ define i32 @test11(i32* %ptr) {
; PPC64LE-LABEL: test11:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
-; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: lwz 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
@@ -167,7 +164,6 @@ define i64 @test15(i64* %ptr) {
; PPC64LE-LABEL: test15:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync
-; PPC64LE-NEXT: ori 2, 2, 0
; PPC64LE-NEXT: ld 3, 0(3)
; PPC64LE-NEXT: cmpd 7, 3, 3
; PPC64LE-NEXT: bne- 7, .+4
Modified: llvm/trunk/test/CodeGen/PowerPC/coldcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/coldcc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/coldcc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/coldcc.ll Wed Jul 4 11:54:25 2018
@@ -30,10 +30,10 @@ entry:
; COLDCC: std 8, -24(1)
; COLDCC: std 9, -32(1)
; COLDCC: std 10, -40(1)
+; COLDCC: ld 10, -40(1)
; COLDCC: ld 9, -32(1)
; COLDCC: ld 8, -24(1)
; COLDCC: ld 7, -16(1)
-; COLDCC: ld 10, -40(1)
; COLDCC: ld 6, -8(1)
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
%mul = mul nsw i32 %a, 3
Modified: llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir Wed Jul 4 11:54:25 2018
@@ -2862,7 +2862,7 @@ body: |
%11 = LI8 280
%12 = LDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10)
; CHECK: LD 280, %0
- ; CHECK-LATE: ld 12, 280(3)
+ ; CHECK-LATE: ld 3, 280(3)
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
BLR8 implicit $lr8, implicit $rm, implicit $x3
Modified: llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll Wed Jul 4 11:54:25 2018
@@ -79,13 +79,13 @@ entry:
; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
-; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: ori r4, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r3, r7, 0
-; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT: addi r4, r5, 0
; CHECK-NEXT: [[SUCCESSOR]]
-; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
}
@@ -104,12 +104,12 @@ entry:
; CHECK: cmpwi cr0, r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
-; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: ori r4, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
-; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT: addi r4, r5, 0
; CHECK-NEXT: [[SUCCESSOR]]
-; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fabs.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fabs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fabs.ll Wed Jul 4 11:54:25 2018
@@ -14,9 +14,7 @@ define float @bitcast_fabs(float %x) {
; CHECK-LABEL: bitcast_fabs:
; CHECK: ; %bb.0:
; CHECK-NEXT: stfs f1, -8(r1)
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: lwz r2, -8(r1)
+; CHECK: lwz r2, -8(r1)
; CHECK-NEXT: clrlwi r2, r2, 1
; CHECK-NEXT: stw r2, -4(r1)
; CHECK-NEXT: lfs f1, -4(r1)
Modified: llvm/trunk/test/CodeGen/PowerPC/fmf-propagation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fmf-propagation.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fmf-propagation.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fmf-propagation.ll Wed Jul 4 11:54:25 2018
@@ -154,7 +154,7 @@ define float @fmul_fadd_fast2(float %x,
; This is the minimum FMF needed for this transform - the FMA allows reassociation.
; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
-; FMFDEBUG: fmul reassoc {{t[0-9]+}},
+; FMFDEBUG: fmul reassoc {{t[0-9]+}},
; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc1:'
; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
@@ -287,25 +287,25 @@ define float @fmul_fma_fast2(float %x) {
define float @sqrt_afn(float %x) {
; FMF-LABEL: sqrt_afn:
-; FMF: # %bb.0:
-; FMF-NEXT: xxlxor 0, 0, 0
-; FMF-NEXT: fcmpu 0, 1, 0
-; FMF-NEXT: beq 0, .LBB10_2
-; FMF-NEXT: # %bb.1:
-; FMF-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
-; FMF-NEXT: xsrsqrtesp 3, 1
-; FMF-NEXT: addi 3, 3, .LCPI10_0 at toc@l
-; FMF-NEXT: lfsx 0, 0, 3
-; FMF-NEXT: xsmulsp 2, 1, 0
-; FMF-NEXT: xsmulsp 4, 3, 3
-; FMF-NEXT: xssubsp 2, 2, 1
-; FMF-NEXT: xsmulsp 2, 2, 4
-; FMF-NEXT: xssubsp 0, 0, 2
-; FMF-NEXT: xsmulsp 0, 3, 0
-; FMF-NEXT: xsmulsp 0, 0, 1
-; FMF-NEXT: .LBB10_2:
-; FMF-NEXT: fmr 1, 0
-; FMF-NEXT: blr
+; FMF: # %bb.0:
+; FMF-NEXT: xxlxor 0, 0, 0
+; FMF-NEXT: fcmpu 0, 1, 0
+; FMF-NEXT: beq 0, .LBB10_2
+; FMF-NEXT: # %bb.1:
+; FMF-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
+; FMF-NEXT: xsrsqrtesp 3, 1
+; FMF-NEXT: addi 3, 3, .LCPI10_0 at toc@l
+; FMF-NEXT: lfsx 0, 0, 3
+; FMF-NEXT: xsmulsp 2, 1, 0
+; FMF-NEXT: xsmulsp 4, 3, 3
+; FMF-NEXT: xssubsp 2, 2, 1
+; FMF-NEXT: xsmulsp 2, 2, 4
+; FMF-NEXT: xssubsp 0, 0, 2
+; FMF-NEXT: xsmulsp 0, 3, 0
+; FMF-NEXT: xsmulsp 0, 0, 1
+; FMF-NEXT: .LBB10_2:
+; FMF-NEXT: fmr 1, 0
+; FMF-NEXT: blr
;
; GLOBAL-LABEL: sqrt_afn:
; GLOBAL: # %bb.0:
@@ -314,8 +314,8 @@ define float @sqrt_afn(float %x) {
; GLOBAL-NEXT: beq 0, .LBB10_2
; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 2, 1
-; GLOBAL-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
; GLOBAL-NEXT: fneg 0, 1
+; GLOBAL-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
; GLOBAL-NEXT: fmr 4, 1
; GLOBAL-NEXT: addi 3, 3, .LCPI10_0 at toc@l
; GLOBAL-NEXT: lfsx 3, 0, 3
@@ -343,25 +343,25 @@ define float @sqrt_afn(float %x) {
define float @sqrt_fast(float %x) {
; FMF-LABEL: sqrt_fast:
-; FMF: # %bb.0:
-; FMF-NEXT: xxlxor 0, 0, 0
-; FMF-NEXT: fcmpu 0, 1, 0
-; FMF-NEXT: beq 0, .LBB11_2
-; FMF-NEXT: # %bb.1:
-; FMF-NEXT: xsrsqrtesp 2, 1
-; FMF-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
-; FMF-NEXT: fneg 0, 1
-; FMF-NEXT: fmr 4, 1
-; FMF-NEXT: addi 3, 3, .LCPI11_0 at toc@l
-; FMF-NEXT: lfsx 3, 0, 3
-; FMF-NEXT: xsmaddasp 4, 0, 3
-; FMF-NEXT: xsmulsp 0, 2, 2
-; FMF-NEXT: xsmaddasp 3, 4, 0
-; FMF-NEXT: xsmulsp 0, 2, 3
-; FMF-NEXT: xsmulsp 0, 0, 1
-; FMF-NEXT: .LBB11_2:
-; FMF-NEXT: fmr 1, 0
-; FMF-NEXT: blr
+; FMF: # %bb.0:
+; FMF-NEXT: xxlxor 0, 0, 0
+; FMF-NEXT: fcmpu 0, 1, 0
+; FMF-NEXT: beq 0, .LBB11_2
+; FMF-NEXT: # %bb.1:
+; FMF-NEXT: xsrsqrtesp 2, 1
+; FMF-NEXT: fneg 0, 1
+; FMF-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
+; FMF-NEXT: fmr 4, 1
+; FMF-NEXT: addi 3, 3, .LCPI11_0 at toc@l
+; FMF-NEXT: lfsx 3, 0, 3
+; FMF-NEXT: xsmaddasp 4, 0, 3
+; FMF-NEXT: xsmulsp 0, 2, 2
+; FMF-NEXT: xsmaddasp 3, 4, 0
+; FMF-NEXT: xsmulsp 0, 2, 3
+; FMF-NEXT: xsmulsp 0, 0, 1
+; FMF-NEXT: .LBB11_2:
+; FMF-NEXT: fmr 1, 0
+; FMF-NEXT: blr
;
; GLOBAL-LABEL: sqrt_fast:
; GLOBAL: # %bb.0:
@@ -370,8 +370,8 @@ define float @sqrt_fast(float %x) {
; GLOBAL-NEXT: beq 0, .LBB11_2
; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 2, 1
-; GLOBAL-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
; GLOBAL-NEXT: fneg 0, 1
+; GLOBAL-NEXT: addis 3, 2, .LCPI11_0 at toc@ha
; GLOBAL-NEXT: fmr 4, 1
; GLOBAL-NEXT: addi 3, 3, .LCPI11_0 at toc@l
; GLOBAL-NEXT: lfsx 3, 0, 3
Modified: llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll Wed Jul 4 11:54:25 2018
@@ -28,7 +28,6 @@ entry:
; PPC32-DAG: stfd 1, 24(1)
; PPC32-DAG: stfd 2, 16(1)
-; PPC32: nop
; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
@@ -70,7 +69,6 @@ entry:
; PPC32-DAG: stfd 1, 24(1)
; PPC32-DAG: stfd 2, 16(1)
-; PPC32: nop
; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
@@ -90,10 +88,10 @@ entry:
; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
-; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
-; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-NOT: BARRIER
+; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
+; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
@@ -103,17 +101,16 @@ entry:
; PPC64-P8-LABEL: test_copysign:
; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
-; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
-; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-P8-NOT: BARRIER
+; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
+; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
; PPC64-P8: blr
; PPC32: stfd 1, [[STACK:[0-9]+]](1)
-; PPC32: nop
; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
; PPC32-NOT: BARRIER
Modified: llvm/trunk/test/CodeGen/PowerPC/fsub-fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fsub-fneg.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fsub-fneg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fsub-fneg.ll Wed Jul 4 11:54:25 2018
@@ -9,8 +9,8 @@ define double @neg_ext_op1_extra_use(flo
; CHECK-LABEL: neg_ext_op1_extra_use:
; CHECK: # %bb.0:
; CHECK-NEXT: xsadddp 0, 2, 1
-; CHECK-NEXT: fneg 13, 1
-; CHECK-NEXT: xsdivdp 1, 13, 0
+; CHECK-NEXT: fneg 1, 1
+; CHECK-NEXT: xsdivdp 1, 1, 0
; CHECK-NEXT: blr
%t1 = fsub float -0.0, %x
%t2 = fpext float %t1 to double
Modified: llvm/trunk/test/CodeGen/PowerPC/i1-ext-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/i1-ext-fold.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/i1-ext-fold.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/i1-ext-fold.ll Wed Jul 4 11:54:25 2018
@@ -19,12 +19,9 @@ entry:
; CHECK: isel 3, [[REG2]], [[REG1]],
; CHECK: blr
-; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: bclr 12, 0, 0
; CHECK-NO-ISEL: ori 3, 5, 0
; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
-; CHECK-NO-ISEL-NEXT: blr
}
; Function Attrs: nounwind readnone
@@ -44,12 +41,9 @@ entry:
; CHECK: isel 3, [[REG2]], [[REG1]],
; CHECK: blr
-; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: bclr 12, 0, 0
; CHECK-NO-ISEL: ori 3, 5, 0
; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
-; CHECK-NO-ISEL-NEXT: blr
}
; Function Attrs: nounwind readnone
Modified: llvm/trunk/test/CodeGen/PowerPC/i1-to-double.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/i1-to-double.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/i1-to-double.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/i1-to-double.ll Wed Jul 4 11:54:25 2018
@@ -6,9 +6,9 @@ define double @test(i1 %X) {
; CHECK-LABEL: @test
-; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK-NEXT: addis 4, 4, .LCPI
+; CHECK: addis 4, 4, .LCPI
; CHECK-NEXT: addis 5, 5, .LCPI
+; CHECK: andi. {{[0-9]+}}, 3, 1
; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
; CHECK: ori 3, 4, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
Modified: llvm/trunk/test/CodeGen/PowerPC/i64_fp_round.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/i64_fp_round.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/i64_fp_round.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/i64_fp_round.ll Wed Jul 4 11:54:25 2018
@@ -21,12 +21,11 @@ entry:
; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori [[REG3:[0-9]+]], 3, 0
-; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi [[REG3]], [[REG2]], 0
+; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0
; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
-; CHECK-NO-ISEL: std [[REG3]], -{{[0-9]+}}(1)
+; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1)
; CHECK: std [[REG3]], -{{[0-9]+}}(1)
Modified: llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/licm-remat.ll Wed Jul 4 11:54:25 2018
@@ -20,8 +20,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(
define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
; CHECK-LABEL: ZN6snappyDecompressor_:
; CHECK: # %bb.0: # %entry
-; CHECK: addis 23, 2, _ZN6snappy8internalL8wordmaskE at toc@ha
-; CHECK-DAG: addi 25, 23, _ZN6snappy8internalL8wordmaskE at toc@l
+; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE at toc@ha
+; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE at toc@l
; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE at toc@ha
; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE at toc@l
; CHECK: b .LBB0_2
Modified: llvm/trunk/test/CodeGen/PowerPC/machine-combiner.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/machine-combiner.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/machine-combiner.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/machine-combiner.ll Wed Jul 4 11:54:25 2018
@@ -68,12 +68,12 @@ define float @reassociate_adds4(float %x
define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
; CHECK-LABEL: reassociate_adds5:
; CHECK: # %bb.0:
-; CHECK: fadds [[REG12:[0-9]+]], 5, 6
-; CHECK: fadds [[REG0:[0-9]+]], 1, 2
-; CHECK: fadds [[REG11:[0-9]+]], 3, 4
+; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 6
+; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 2
+; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 4
; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7
-; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
-; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
+; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
+; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
; CHECK: fadds 1, [[REG2]], 8
; CHECK-NEXT: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll Wed Jul 4 11:54:25 2018
@@ -107,9 +107,9 @@ define signext i32 @zeroEqualityTest04()
; CHECK-NEXT: beq 0, .LBB3_3
; CHECK-NEXT: .LBB3_2: # %res_block
; CHECK-NEXT: cmpld 3, 4
-; CHECK-NEXT: li 11, 1
-; CHECK-NEXT: li 12, -1
-; CHECK-NEXT: isel 5, 12, 11, 0
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: isel 5, 4, 3, 0
; CHECK-NEXT: .LBB3_3: # %endblock
; CHECK-NEXT: extsw 3, 5
; CHECK-NEXT: neg 3, 3
@@ -143,9 +143,9 @@ define signext i32 @zeroEqualityTest05()
; CHECK-NEXT: beq 0, .LBB4_3
; CHECK-NEXT: .LBB4_2: # %res_block
; CHECK-NEXT: cmpld 3, 4
-; CHECK-NEXT: li 11, 1
-; CHECK-NEXT: li 12, -1
-; CHECK-NEXT: isel 5, 12, 11, 0
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: isel 5, 4, 3, 0
; CHECK-NEXT: .LBB4_3: # %endblock
; CHECK-NEXT: srwi 3, 5, 31
; CHECK-NEXT: xori 3, 3, 1
@@ -172,8 +172,8 @@ define signext i32 @equalityFoldTwoConst
define signext i32 @equalityFoldOneConstant(i8* %X) {
; CHECK-LABEL: equalityFoldOneConstant:
; CHECK: # %bb.0:
-; CHECK-NEXT: li 5, 1
; CHECK-NEXT: ld 4, 0(3)
+; CHECK-NEXT: li 5, 1
; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: cmpld 4, 5
; CHECK-NEXT: bne 0, .LBB6_2
Modified: llvm/trunk/test/CodeGen/PowerPC/p8-isel-sched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/p8-isel-sched.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/p8-isel-sched.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/p8-isel-sched.ll Wed Jul 4 11:54:25 2018
@@ -28,17 +28,15 @@ entry:
; CHECK-NO-ISEL-LABEL: @foo
; CHECK: isel
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 7, 12, 0
-; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 7, 11, 0
+; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, {{[0-9]+}}, 0
; CHECK: addi
; CHECK: isel
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 10, 11, 0
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 10, 12, 0
; CHECK: blr
attributes #0 = { nounwind }
Modified: llvm/trunk/test/CodeGen/PowerPC/peephole-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/peephole-align.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/peephole-align.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/peephole-align.ll Wed Jul 4 11:54:25 2018
@@ -239,8 +239,8 @@ entry:
; Make sure the optimization fails to fire if the symbol is aligned, but the offset is not.
; CHECK-LABEL: test_misalign
; CHECK: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v at toc@ha
-; CHECK: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v at toc@l
-; CHECK: li [[OFFSET_REG:[0-9]+]], 1
+; CHECK-DAG: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v at toc@l
+; CHECK-DAG: li [[OFFSET_REG:[0-9]+]], 1
; CHECK: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]]
; CHECK: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
; CHECK: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]]
Modified: llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppcf128-endian.ll Wed Jul 4 11:54:25 2018
@@ -105,9 +105,8 @@ entry:
ret ppc_fp128 %0
}
; CHECK: convert_to:
-; CHECK: std 3, [[OFF1:.*]](1)
-; CHECK: std 4, [[OFF2:.*]](1)
-; CHECK: ori 2, 2, 0
+; CHECK-DAG: std 3, [[OFF1:.*]](1)
+; CHECK-DAG: std 4, [[OFF2:.*]](1)
; CHECK: lfd 1, [[OFF1]](1)
; CHECK: lfd 2, [[OFF2]](1)
; CHECK: blr
@@ -122,7 +121,6 @@ entry:
; CHECK: convert_to2:
; CHECK: std 3, [[OFF1:.*]](1)
; CHECK: std 5, [[OFF2:.*]](1)
-; CHECK: ori 2, 2, 0
; CHECK: lfd 1, [[OFF1]](1)
; CHECK: lfd 2, [[OFF2]](1)
; CHECK: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/pr27078.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr27078.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr27078.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr27078.ll Wed Jul 4 11:54:25 2018
@@ -10,8 +10,8 @@ define <4 x float> @bar(float* %p, float
ret <4 x float> %6
; CHECK: xxsldwi
-; CHECK-NEXT: vmrghw
-; CHECK-NEXT: vmrglw
+; CHECK-DAG: vmrghw
+; CHECK-DAG: vmrglw
; CHECK-NEXT: xxsldwi
; CHECK-NEXT: xxsldwi
; CHECK-NEXT: xxsldwi
Modified: llvm/trunk/test/CodeGen/PowerPC/pr33093.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr33093.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr33093.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr33093.ll Wed Jul 4 11:54:25 2018
@@ -9,27 +9,27 @@ define zeroext i32 @ReverseBits(i32 zero
; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1
-; CHECK-NEXT: lis 7, -13108
-; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
-; CHECK-NEXT: lis 10, -3856
-; CHECK-NEXT: lis 11, 3855
-; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: and 4, 6, 4
-; CHECK-NEXT: ori 5, 8, 13107
+; CHECK-NEXT: and 3, 3, 5
+; CHECK-NEXT: lis 5, 13107
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: ori 4, 7, 52428
-; CHECK-NEXT: slwi 9, 3, 2
+; CHECK-NEXT: lis 4, -13108
+; CHECK-NEXT: ori 5, 5, 13107
+; CHECK-NEXT: slwi 6, 3, 2
+; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: srwi 3, 3, 2
+; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
-; CHECK-NEXT: and 4, 9, 4
-; CHECK-NEXT: ori 5, 11, 3855
+; CHECK-NEXT: lis 5, 3855
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: ori 4, 10, 61680
-; CHECK-NEXT: slwi 12, 3, 4
+; CHECK-NEXT: lis 4, -3856
+; CHECK-NEXT: ori 5, 5, 3855
+; CHECK-NEXT: slwi 6, 3, 4
+; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: srwi 3, 3, 4
-; CHECK-NEXT: and 4, 12, 4
+; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24
@@ -85,41 +85,41 @@ define i64 @ReverseBits64(i64 %n) {
; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
+; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32
; CHECK-NEXT: sldi 6, 7, 32
-; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: lis 7, 3855
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: oris 9, 5, 52428
-; CHECK-NEXT: oris 10, 6, 13107
+; CHECK-NEXT: oris 4, 5, 52428
+; CHECK-NEXT: oris 5, 6, 13107
; CHECK-NEXT: lis 6, -3856
; CHECK-NEXT: ori 7, 7, 3855
; CHECK-NEXT: sldi 8, 3, 2
-; CHECK-NEXT: ori 4, 9, 52428
+; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: rldicl 3, 3, 62, 2
-; CHECK-NEXT: ori 5, 10, 13107
+; CHECK-NEXT: ori 5, 5, 13107
; CHECK-NEXT: ori 6, 6, 61680
+; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32
-; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: sldi 6, 7, 32
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: oris 11, 5, 61680
-; CHECK-NEXT: oris 12, 6, 3855
+; CHECK-NEXT: oris 4, 5, 61680
+; CHECK-NEXT: oris 5, 6, 3855
; CHECK-NEXT: sldi 6, 3, 4
-; CHECK-NEXT: ori 4, 11, 61680
+; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: rldicl 3, 3, 60, 4
-; CHECK-NEXT: ori 5, 12, 3855
+; CHECK-NEXT: ori 5, 5, 3855
; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rldicl 4, 3, 32, 32
+; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
-; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
+; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6
Modified: llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll Wed Jul 4 11:54:25 2018
@@ -18,10 +18,8 @@ entry:
; CHECK: lfs [[REG1:[0-9]+]], 0(4)
; CHECK: stfs [[REG1]], 0(3)
-; CHECK: ori 2, 2, 0
; CHECK: lfs [[REG2:[0-9]+]], 0(5)
; CHECK: stfs [[REG2]], 0(4)
-; CHECK: ori 2, 2, 0
; CHECK: lfs [[REG3:[0-9]+]], 0(3)
; CHECK: stfs [[REG3]], 0(6)
; CHECK: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/qpx-recipest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/qpx-recipest.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/qpx-recipest.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/qpx-recipest.ll Wed Jul 4 11:54:25 2018
@@ -14,11 +14,11 @@ entry:
; CHECK-LABEL: @foo
; CHECK: qvfrsqrte
-; CHECK: qvfmul
+; CHECK-DAG: qvfmul
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
; an qvfmadd instead of a qvfnmsub
-; CHECK: qvfmadd
-; CHECK: qvfmadd
+; CHECK-DAG: qvfmadd
+; CHECK-DAG: qvfmadd
; CHECK: qvfmul
; CHECK: qvfmul
; CHECK: qvfmadd
@@ -41,11 +41,11 @@ entry:
; CHECK-LABEL: @foof
; CHECK: qvfrsqrtes
-; CHECK: qvfmuls
+; CHECK-DAG: qvfmuls
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
; an qvfmadd instead of a qvfnmsubs
-; CHECK: qvfmadds
-; CHECK: qvfmadds
+; CHECK-DAG: qvfmadds
+; CHECK-DAG: qvfmadds
; CHECK: qvfmuls
; CHECK: qvfmul
; CHECK: blr
@@ -65,11 +65,11 @@ entry:
; CHECK-LABEL: @food
; CHECK: qvfrsqrte
-; CHECK: qvfmul
+; CHECK-DAG: qvfmul
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
; an qvfmadd instead of a qvfnmsub
-; CHECK: qvfmadd
-; CHECK: qvfmadd
+; CHECK-DAG: qvfmadd
+; CHECK-DAG: qvfmadd
; CHECK: qvfmul
; CHECK: qvfmul
; CHECK: qvfmadd
@@ -92,11 +92,11 @@ entry:
; CHECK-LABEL: @goo
; CHECK: qvfrsqrtes
-; CHECK: qvfmuls
+; CHECK-DAG: qvfmuls
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
; an qvfmadd instead of a qvfnmsubs
-; CHECK: qvfmadds
-; CHECK: qvfmadds
+; CHECK-DAG: qvfmadds
+; CHECK-DAG: qvfmadds
; CHECK: qvfmuls
; CHECK: qvfmuls
; CHECK: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll Wed Jul 4 11:54:25 2018
@@ -6,8 +6,8 @@
; CHECK: stwu 1, -32(1)
; CHECK: stw 31, 28(1)
; CHECK: mr 31, 1
-; CHECK: stw 30, 24(1)
-; CHECK: mfcr [[CR:[0-9]+]]
+; CHECK-DAG: stw 30, 24(1)
+; CHECK-DAG: mfcr [[CR:[0-9]+]]
; CHECK: stw [[CR]], 20(31)
target datalayout = "E-m:e-p:32:32-i64:64-n32"
Modified: llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll Wed Jul 4 11:54:25 2018
@@ -21,8 +21,8 @@ define float @testMultipleAccess(i32* no
; CHECK-LABEL: testMultipleAccess:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 4, 8(3)
-; CHECK-NEXT: lwz 12, 12(3)
-; CHECK-NEXT: add 3, 12, 4
+; CHECK-NEXT: lwz 3, 12(3)
+; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: mtvsrwa 0, 3
; CHECK-NEXT: xscvsxdsp 1, 0
; CHECK-NEXT: blr
Modified: llvm/trunk/test/CodeGen/PowerPC/select_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/select_const.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/select_const.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/select_const.ll Wed Jul 4 11:54:25 2018
@@ -695,25 +695,25 @@ define i8 @sel_constants_xor_constant(i1
define i8 @sel_constants_shl_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_shl_constant:
; ISEL: # %bb.0:
-; ISEL-NEXT: lis 5, 511
; ISEL-NEXT: lis 4, 2047
+; ISEL-NEXT: lis 5, 511
; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: ori 3, 4, 65535
-; ISEL-NEXT: ori 12, 5, 65535
+; ISEL-NEXT: ori 4, 5, 65535
; ISEL-NEXT: sldi 3, 3, 5
-; ISEL-NEXT: sldi 4, 12, 7
+; ISEL-NEXT: sldi 4, 4, 7
; ISEL-NEXT: isel 3, 4, 3, 1
; ISEL-NEXT: blr
;
; NO_ISEL-LABEL: sel_constants_shl_constant:
; NO_ISEL: # %bb.0:
-; NO_ISEL-NEXT: lis 5, 511
; NO_ISEL-NEXT: lis 4, 2047
+; NO_ISEL-NEXT: lis 5, 511
; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: ori 3, 4, 65535
-; NO_ISEL-NEXT: ori 12, 5, 65535
+; NO_ISEL-NEXT: ori 4, 5, 65535
; NO_ISEL-NEXT: sldi 3, 3, 5
-; NO_ISEL-NEXT: sldi 4, 12, 7
+; NO_ISEL-NEXT: sldi 4, 4, 7
; NO_ISEL-NEXT: bc 12, 1, .LBB36_1
; NO_ISEL-NEXT: blr
; NO_ISEL-NEXT: .LBB36_1:
Modified: llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/setcc-logic.ll Wed Jul 4 11:54:25 2018
@@ -86,7 +86,7 @@ define zeroext i1 @any_bits_clear(i32 %P
; CHECK-NEXT: li 5, -1
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: xor 3, 3, 5
-; CHECK-NEXT: cntlzw 3, 3
+; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
; CHECK-NEXT: xori 3, 3, 1
; CHECK-NEXT: blr
@@ -469,8 +469,8 @@ define <4 x i1> @and_eq_vec(<4 x i32> %a
; CHECK-LABEL: and_eq_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
-; CHECK-NEXT: vcmpequw 19, 4, 5
-; CHECK-NEXT: xxland 34, 34, 51
+; CHECK-NEXT: vcmpequw 3, 4, 5
+; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%cmp1 = icmp eq <4 x i32> %a, %b
%cmp2 = icmp eq <4 x i32> %c, %d
Modified: llvm/trunk/test/CodeGen/PowerPC/shift128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/shift128.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/shift128.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/shift128.ll Wed Jul 4 11:54:25 2018
@@ -26,7 +26,7 @@ define i128 @lshr(i128 %x, i128 %y) {
; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
; CHECK-DAG: cmpwi [[R1]], 1
; CHECK-DAG: srad 4, 4, 5
-; CHECK: isel 3, [[R5]], [[R4]], 0
+; CHECK-DAG: isel 3, [[R5]], [[R4]], 0
; CHECK: blr
define i128 @ashr(i128 %x, i128 %y) {
%r = ashr i128 %x, %y
Modified: llvm/trunk/test/CodeGen/PowerPC/store-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/store-constant.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/store-constant.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/store-constant.ll Wed Jul 4 11:54:25 2018
@@ -44,10 +44,10 @@ define void @bar(%struct.S* %p) {
; CHECK-LABEL: @bar
; CHECK: li 4, 2
-; CHECK: stw 4, 12(3)
-; CHECK: sth 4, 10(3)
-; CHECK: std 4, 0(3)
-; CHECK: stb 4, 8(3)
+; CHECK-DAG: stw 4, 12(3)
+; CHECK-DAG: sth 4, 10(3)
+; CHECK-DAG: std 4, 0(3)
+; CHECK-DAG: stb 4, 8(3)
}
; Function Attrs: norecurse nounwind
Modified: llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll Wed Jul 4 11:54:25 2018
@@ -12,15 +12,15 @@
; CHECK: xxspltd
; CHECK-NEXT: xxspltd
; CHECK-NEXT: xvmuldp
-; CHECK-NEXT: xvmuldp
-; CHECK-NEXT: xvsubdp
-; CHECK-NEXT: xvadddp
-; CHECK-NEXT: xxswapd
-; CHECK-NEXT: xxpermdi
-; CHECK-NEXT: xvsubdp
-; CHECK-NEXT: xxswapd
+; CHECK-DAG: xvmuldp
+; CHECK-DAG: xvsubdp
+; CHECK-DAG: xvadddp
+; CHECK-DAG: xxswapd
+; CHECK-DAG: xxpermdi
+; CHECK-DAG: xvsubdp
+; CHECK: xxswapd
; CHECK-NEXT: stxvd2x
-; CHECK-NEXT: blr
+; CHECK: blr
; Function Attrs: noinline
define void @zg(i8* %.G0011_640.0, i8* %.G0012_642.0, <2 x double>* %JJ, <2 x double>* %.ka0000_391, double %.unpack, double %.unpack66) #0 {
Modified: llvm/trunk/test/CodeGen/PowerPC/testBitReverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testBitReverse.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testBitReverse.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testBitReverse.ll Wed Jul 4 11:54:25 2018
@@ -9,27 +9,27 @@ define i32 @testBitReverseIntrinsicI32(i
; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1
-; CHECK-NEXT: lis 7, -13108
-; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
-; CHECK-NEXT: lis 10, -3856
-; CHECK-NEXT: lis 11, 3855
-; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: and 4, 6, 4
-; CHECK-NEXT: ori 5, 8, 13107
+; CHECK-NEXT: and 3, 3, 5
+; CHECK-NEXT: lis 5, 13107
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: ori 4, 7, 52428
-; CHECK-NEXT: slwi 9, 3, 2
+; CHECK-NEXT: lis 4, -13108
+; CHECK-NEXT: ori 5, 5, 13107
+; CHECK-NEXT: slwi 6, 3, 2
+; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: srwi 3, 3, 2
+; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
-; CHECK-NEXT: and 4, 9, 4
-; CHECK-NEXT: ori 5, 11, 3855
+; CHECK-NEXT: lis 5, 3855
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: ori 4, 10, 61680
-; CHECK-NEXT: slwi 12, 3, 4
+; CHECK-NEXT: lis 4, -3856
+; CHECK-NEXT: ori 5, 5, 3855
+; CHECK-NEXT: slwi 6, 3, 4
+; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: srwi 3, 3, 4
-; CHECK-NEXT: and 4, 12, 4
+; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24
@@ -61,41 +61,41 @@ define i64 @testBitReverseIntrinsicI64(i
; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
+; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32
; CHECK-NEXT: sldi 6, 7, 32
-; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: lis 7, 3855
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: oris 9, 5, 52428
-; CHECK-NEXT: oris 10, 6, 13107
+; CHECK-NEXT: oris 4, 5, 52428
+; CHECK-NEXT: oris 5, 6, 13107
; CHECK-NEXT: lis 6, -3856
; CHECK-NEXT: ori 7, 7, 3855
; CHECK-NEXT: sldi 8, 3, 2
-; CHECK-NEXT: ori 4, 9, 52428
+; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: rldicl 3, 3, 62, 2
-; CHECK-NEXT: ori 5, 10, 13107
+; CHECK-NEXT: ori 5, 5, 13107
; CHECK-NEXT: ori 6, 6, 61680
+; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32
-; CHECK-NEXT: and 4, 8, 4
; CHECK-NEXT: sldi 6, 7, 32
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: oris 11, 5, 61680
-; CHECK-NEXT: oris 12, 6, 3855
+; CHECK-NEXT: oris 4, 5, 61680
+; CHECK-NEXT: oris 5, 6, 3855
; CHECK-NEXT: sldi 6, 3, 4
-; CHECK-NEXT: ori 4, 11, 61680
+; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: rldicl 3, 3, 60, 4
-; CHECK-NEXT: ori 5, 12, 3855
+; CHECK-NEXT: ori 5, 5, 3855
; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
-; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rldicl 4, 3, 32, 32
+; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
-; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
+; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsc.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_ieqsc_store(i8 signext
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsi.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_ieqsi_store(i32 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqsll.ll Wed Jul 4 11:54:25 2018
@@ -69,10 +69,10 @@ define void @test_ieqsll_store(i64 %a, i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@@ -87,10 +87,10 @@ define void @test_ieqsll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesieqss.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_ieqss_store(i16 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequc.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_iequc_store(i8 zeroext
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequi.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_iequi_store(i32 zeroex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequll.ll Wed Jul 4 11:54:25 2018
@@ -69,10 +69,10 @@ define void @test_iequll_store(i64 %a, i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@@ -87,10 +87,10 @@ define void @test_iequll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiequs.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_iequs_store(i16 zeroex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll Wed Jul 4 11:54:25 2018
@@ -38,10 +38,10 @@ define void @test_igesc_store(i8 signext
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
@@ -55,10 +55,10 @@ define void @test_igesc_sext_store(i8 si
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
@@ -38,10 +38,10 @@ define void @test_igesi_store(i32 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
@@ -55,10 +55,10 @@ define void @test_igesi_sext_store(i32 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll Wed Jul 4 11:54:25 2018
@@ -38,10 +38,10 @@ define void @test_igess_store(i16 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
@@ -55,10 +55,10 @@ define void @test_igess_sext_store(i16 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
@@ -38,10 +38,10 @@ define void @test_ilesc_store(i8 signext
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
@@ -55,10 +55,10 @@ define void @test_ilesc_sext_store(i8 si
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
@@ -38,10 +38,10 @@ define void @test_ilesi_store(i32 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
@@ -55,10 +55,10 @@ define void @test_ilesi_sext_store(i32 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesll.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ilesll(i64 %a, i64 %b) {
@@ -12,7 +12,7 @@ define signext i32 @test_ilesll(i64 %a,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
@@ -26,7 +26,7 @@ define signext i32 @test_ilesll_sext(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
@@ -65,11 +65,13 @@ entry:
define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK: subfc r4, r3, r4
-; CHECK: rldicl r3, r3, 1, 63
-; CHECK: adde r3, r6, r3
-; CHECK: std r3,
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@@ -81,12 +83,14 @@ entry:
define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK-DAG: rldicl r3, r3, 1, 63
-; CHECK-DAG: subfc r4, r3, r4
-; CHECK: adde r3, r6, r3
-; CHECK: neg r3, r3
-; CHECK: std r3,
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
@@ -38,10 +38,10 @@ define void @test_iless_store(i16 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
@@ -55,10 +55,10 @@ define void @test_iless_sext_store(i16 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesinesll.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
@@ -63,10 +63,10 @@ define void @test_inesll_store(i64 %a, i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@@ -80,10 +80,10 @@ define void @test_inesll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineuc.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
@@ -66,8 +66,8 @@ entry:
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineull.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
@@ -63,10 +63,10 @@ define void @test_ineull_store(i64 %a, i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@@ -80,10 +80,10 @@ define void @test_ineull_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesineus.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
@@ -67,8 +67,8 @@ entry:
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsc.ll Wed Jul 4 11:54:25 2018
@@ -71,10 +71,10 @@ define void @test_lleqsc_store(i8 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@@ -87,8 +87,8 @@ entry:
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsi.ll Wed Jul 4 11:54:25 2018
@@ -70,10 +70,10 @@ define void @test_lleqsi_store(i32 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@@ -86,8 +86,8 @@ entry:
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqsll.ll Wed Jul 4 11:54:25 2018
@@ -68,10 +68,10 @@ define void @test_lleqsll_store(i64 %a,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@@ -86,10 +86,10 @@ define void @test_lleqsll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslleqss.ll Wed Jul 4 11:54:25 2018
@@ -70,10 +70,10 @@ define void @test_lleqss_store(i16 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@@ -86,8 +86,8 @@ entry:
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequc.ll Wed Jul 4 11:54:25 2018
@@ -70,10 +70,10 @@ define void @test_llequc_store(i8 zeroex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
@@ -86,8 +86,8 @@ entry:
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequi.ll Wed Jul 4 11:54:25 2018
@@ -70,10 +70,10 @@ define void @test_llequi_store(i32 zeroe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
@@ -86,8 +86,8 @@ entry:
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequll.ll Wed Jul 4 11:54:25 2018
@@ -68,10 +68,10 @@ define void @test_llequll_store(i64 %a,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
@@ -86,10 +86,10 @@ define void @test_llequll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllequs.ll Wed Jul 4 11:54:25 2018
@@ -70,10 +70,10 @@ define void @test_llequs_store(i16 zeroe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
@@ -86,8 +86,8 @@ entry:
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
@@ -38,10 +38,10 @@ define void @test_llgesc_store(i8 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
@@ -55,10 +55,10 @@ define void @test_llgesc_sext_store(i8 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
@@ -38,10 +38,10 @@ define void @test_llgesi_store(i32 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
@@ -55,10 +55,10 @@ define void @test_llgesi_sext_store(i32
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llgess(i16 signext %a, i16 signext %b) {
@@ -38,10 +38,10 @@ define void @test_llgess_store(i16 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
@@ -55,10 +55,10 @@ define void @test_llgess_sext_store(i16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
@@ -39,10 +39,10 @@ define void @test_lllesc_store(i8 signex
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
@@ -56,10 +56,10 @@ define void @test_lllesc_sext_store(i8 s
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stb r3, 0(r12)
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
@@ -39,10 +39,10 @@ define void @test_lllesi_store(i32 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
@@ -56,10 +56,10 @@ define void @test_lllesi_sext_store(i32
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: stw r3, 0(r12)
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesll.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
@@ -13,7 +13,7 @@ define i64 @test_lllesll(i64 %a, i64 %b)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
@@ -28,7 +28,7 @@ define i64 @test_lllesll_sext(i64 %a, i6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
-; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
@@ -70,11 +70,13 @@ entry:
define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK: subfc r4, r3, r4
-; CHECK: rldicl r3, r3, 1, 63
-; CHECK: adde r3, r6, r3
-; CHECK: std r3,
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
@@ -87,12 +89,14 @@ entry:
define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi r6, r4, 63
-; CHECK-DAG: rldicl r3, r3, 1, 63
-; CHECK-DAG: subfc r4, r3, r4
-; CHECK: adde r3, r6, r3
-; CHECK: neg r3, r3
-; CHECK: std r3, 0(r4)
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
@@ -39,10 +39,10 @@ define void @test_llless_store(i16 signe
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
@@ -56,10 +56,10 @@ define void @test_llless_sext_store(i16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: sub r3, r4, r3
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
-; CHECK-NEXT: sth r3, 0(r12)
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllnesll.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
@@ -63,10 +63,10 @@ define void @test_llnesll_store(i64 %a,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@@ -80,10 +80,10 @@ define void @test_llnesll_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllneull.ll Wed Jul 4 11:54:25 2018
@@ -1,10 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
@@ -63,10 +63,10 @@ define void @test_llneull_store(i64 %a,
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
@@ -80,10 +80,10 @@ define void @test_llneull_sext_store(i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
-; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
Modified: llvm/trunk/test/CodeGen/PowerPC/unal-vec-ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/unal-vec-ldst.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/unal-vec-ldst.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/unal-vec-ldst.ll Wed Jul 4 11:54:25 2018
@@ -28,8 +28,8 @@ entry:
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
-; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
+; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
+; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
; CHECK: blr
}
@@ -59,8 +59,8 @@ entry:
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
-; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
+; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
+; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
; CHECK: blr
}
@@ -90,8 +90,8 @@ entry:
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
-; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
+; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
+; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
; CHECK: blr
}
@@ -143,8 +143,8 @@ entry:
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
-; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
+; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
+; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
; CHECK: blr
}
@@ -328,8 +328,8 @@ entry:
; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: qvlpclsx [[REG5:[0-5]+]], 0, 3
; CHECK-DAG: qvlfsx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
-; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
+; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
+; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
; CHECK: blr
}
@@ -359,8 +359,8 @@ entry:
; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 3, [[REG2]]
; CHECK-DAG: qvlpcldx [[REG5:[0-5]+]], 0, 3
; CHECK-DAG: qvlfdx [[REG6:[0-9]+]], 0, 3
-; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
-; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
+; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
+; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/vselect-constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vselect-constants.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vselect-constants.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vselect-constants.ll Wed Jul 4 11:54:25 2018
@@ -16,12 +16,12 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x
; CHECK-NEXT: addis 4, 2, .LCPI0_1 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI0_0 at toc@l
; CHECK-NEXT: addi 4, 4, .LCPI0_1 at toc@l
-; CHECK-NEXT: lvx 18, 0, 3
-; CHECK-NEXT: lvx 19, 0, 4
; CHECK-NEXT: vsubuwm 3, 4, 3
+; CHECK-NEXT: lvx 4, 0, 4
; CHECK-NEXT: vslw 2, 2, 3
; CHECK-NEXT: vsraw 2, 2, 3
-; CHECK-NEXT: xxsel 34, 51, 50, 34
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: xxsel 34, 36, 35, 34
; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add
@@ -35,9 +35,9 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<
; CHECK-NEXT: addis 4, 2, .LCPI1_1 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI1_0 at toc@l
; CHECK-NEXT: addi 4, 4, .LCPI1_1 at toc@l
-; CHECK-NEXT: lvx 19, 0, 3
+; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: lvx 4, 0, 4
-; CHECK-NEXT: xxsel 34, 36, 51, 34
+; CHECK-NEXT: xxsel 34, 36, 35, 34
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
@@ -50,9 +50,9 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4
; CHECK-NEXT: vspltisw 3, 1
; CHECK-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI2_0 at toc@l
-; CHECK-NEXT: lvx 19, 0, 3
; CHECK-NEXT: xxland 34, 34, 35
-; CHECK-NEXT: vadduwm 2, 2, 19
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
ret <4 x i32> %add
@@ -64,8 +64,8 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_ve
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI3_0 at toc@l
-; CHECK-NEXT: lvx 19, 0, 3
-; CHECK-NEXT: vsubuwm 2, 19, 2
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
@@ -79,11 +79,11 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<
; CHECK-NEXT: vspltisw 4, 15
; CHECK-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI4_0 at toc@l
-; CHECK-NEXT: lvx 19, 0, 3
; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vslw 2, 2, 3
; CHECK-NEXT: vsraw 2, 2, 3
-; CHECK-NEXT: vadduwm 2, 2, 19
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
ret <4 x i32> %add
@@ -95,8 +95,8 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_v
; CHECK-NEXT: vcmpequw 2, 2, 3
; CHECK-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI5_0 at toc@l
-; CHECK-NEXT: lvx 19, 0, 3
-; CHECK-NEXT: vadduwm 2, 2, 19
+; CHECK-NEXT: lvx 3, 0, 3
+; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
@@ -163,8 +163,8 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4
; CHECK-LABEL: cmp_sel_1_or_0_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
-; CHECK-NEXT: vspltisw 19, 1
-; CHECK-NEXT: xxland 34, 34, 51
+; CHECK-NEXT: vspltisw 3, 1
+; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
@@ -185,9 +185,9 @@ define <4 x i32> @cmp_sel_0_or_1_vec(<4
; CHECK-LABEL: cmp_sel_0_or_1_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: vcmpequw 2, 2, 3
-; CHECK-NEXT: vspltisw 19, 1
+; CHECK-NEXT: vspltisw 3, 1
; CHECK-NEXT: xxlnor 0, 34, 34
-; CHECK-NEXT: xxland 34, 0, 51
+; CHECK-NEXT: xxland 34, 0, 35
; CHECK-NEXT: blr
%cond = icmp eq <4 x i32> %x, %y
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
Modified: llvm/trunk/test/CodeGen/PowerPC/vsx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx.ll Wed Jul 4 11:54:25 2018
@@ -1137,10 +1137,10 @@ define <2 x i32> @test80(i32 %v) {
ret <2 x i32> %i
; CHECK-REG-LABEL: @test80
-; CHECK-REG: stw 3, -16(1)
-; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
+; CHECK-REG-DAG: stw 3, -16(1)
+; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16
; CHECK-REG: addis [[R2:[0-9]+]]
-; CHECK-REG: addi [[R2]], [[R2]]
+; CHECK-REG-DAG: addi [[R2]], [[R2]]
; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
; CHECK-REG: xxspltw 34, [[VS1]], 0
Modified: llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll?rev=336295&r1=336294&r2=336295&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vsxD-Form-spills.ll Wed Jul 4 11:54:25 2018
@@ -4,34 +4,36 @@
define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: testSpill:
-; CHECK: li 11, 80
-; CHECK: li 12, 96
-; CHECK: li 3, 48
-; CHECK: li 10, 64
-; CHECK: stxvd2x 62, 1, 11 # 16-byte Folded Spill
-; CHECK: stxvd2x 63, 1, 12 # 16-byte Folded Spill
-; CHECK: stxvd2x 60, 1, 3 # 16-byte Folded Spill
-; CHECK: stxvd2x 61, 1, 10 # 16-byte Folded Spill
-; CHECK: li 9, 96
-; CHECK: li 10, 80
-; CHECK: li 11, 64
-; CHECK: li 12, 48
-; CHECK: lxvd2x 63, 1, 9 # 16-byte Folded Reload
-; CHECK: lxvd2x 62, 1, 10 # 16-byte Folded Reload
-; CHECK: lxvd2x 61, 1, 11 # 16-byte Folded Reload
-; CHECK: lxvd2x 60, 1, 12 # 16-byte Folded Reload
+; CHECK-DAG: li [[REG48:[0-9]+]], 48
+; CHECK-DAG: li [[REG64:[0-9]+]], 64
+; CHECK-DAG: li [[REG80:[0-9]+]], 80
+; CHECK-DAG: li [[REG96:[0-9]+]], 96
+; CHECK-DAG: stxvd2x 60, 1, [[REG48]] # 16-byte Folded Spill
+; CHECK-DAG: stxvd2x 61, 1, [[REG64]] # 16-byte Folded Spill
+; CHECK-DAG: stxvd2x 62, 1, [[REG80]] # 16-byte Folded Spill
+; CHECK-DAG: stxvd2x 63, 1, [[REG96]] # 16-byte Folded Spill
+; CHECK: .LBB0_3
+; CHECK-DAG: li [[REG96_LD:[0-9]+]], 96
+; CHECK-DAG: li [[REG80_LD:[0-9]+]], 80
+; CHECK-DAG: li [[REG64_LD:[0-9]+]], 64
+; CHECK-DAG: li [[REG48_LD:[0-9]+]], 48
+; CHECK-DAG: lxvd2x 63, 1, [[REG96_LD]] # 16-byte Folded Reload
+; CHECK-DAG: lxvd2x 62, 1, [[REG80_LD]] # 16-byte Folded Reload
+; CHECK-DAG: lxvd2x 61, 1, [[REG64_LD]] # 16-byte Folded Reload
+; CHECK-DAG: lxvd2x 60, 1, [[REG48_LD]] # 16-byte Folded Reload
; CHECK: mtlr 0
; CHECK-NEXT: blr
;
; CHECK-PWR9-LABEL: testSpill:
-; CHECK-PWR9: stxv 62, 64(1) # 16-byte Folded Spill
-; CHECK-PWR9: stxv 63, 80(1) # 16-byte Folded Spill
-; CHECK-PWR9: stxv 60, 32(1) # 16-byte Folded Spill
-; CHECK-PWR9: stxv 61, 48(1) # 16-byte Folded Spill
-; CHECK-PWR9: lxv 63, 80(1) # 16-byte Folded Reload
-; CHECK-PWR9: lxv 62, 64(1) # 16-byte Folded Reload
-; CHECK-PWR9: lxv 61, 48(1) # 16-byte Folded Reload
-; CHECK-PWR9: lxv 60, 32(1) # 16-byte Folded Reload
+; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill
+; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill
+; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill
+; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill
+; CHECK-PWR9-NOT: NOT
+; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload
+; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload
+; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload
+; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload
; CHECK-PWR9: mtlr 0
; CHECK-PWR9-NEXT: blr
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