[PATCH] D48925: X86: add alias for pushfw/popfw in Intel mode

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: hiraditya, mcrosier.

A while ago we changed pushf and popf in Intel mode to generate pushfq and popfq. Unfortunately that left us with no way to get the 16-bit encoding in Intel mode so this patch adds pushfw and popfw as aliases there.

An alternative would be to revert that change (& make sure both are accessible). The reasoning behind the change was discussed a bit in https://bugs.llvm.org/show_bug.cgi?id=32035 and seems to have been motivated primarily by GCC compatiblity (nasm is the same, masm appears to be the opposite).

Technically, I suspect the Intel & AMD manuals would disagree with the status-quo:

  + They don't mention pushfw at all, which would now be the only way to get the 16-bit instruction.
  + The table part of the descriptions says pushf is 16-bit (and pushfq is 64-bit).
  + Conversely the description talks of 64-bits being the default, but in terms of opcode prefixes rather than mnemonics so I'm not sure how much weight it has.
  + The 32-bit paragraph seems to allow multiple variants.

But GCC compatibility is a pretty compelling counter-argument for me, which is why I'm suggesting this fix for the situation.


Repository:
  rL LLVM

https://reviews.llvm.org/D48925

Files:
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/test/MC/X86/intel-syntax-encoding.s


Index: llvm/test/MC/X86/intel-syntax-encoding.s
===================================================================
--- llvm/test/MC/X86/intel-syntax-encoding.s
+++ llvm/test/MC/X86/intel-syntax-encoding.s
@@ -64,6 +64,11 @@
 pushf
 popf
 
+// CHECK: encoding: [0x66,0x9c]
+// CHECK: encoding: [0x66,0x9d]
+pushfw
+popfw
+
 LBB0_3:
 // CHECK: encoding: [0xeb,A]
 	jmp	LBB0_3
Index: llvm/lib/Target/X86/X86InstrInfo.td
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -2973,6 +2973,8 @@
 def : MnemonicAlias<"popf",  "popfq", "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popf",  "popfq", "intel">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popfd", "popfl", "att">;
+def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In32BitMode]>;
+def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In64BitMode]>;
 
 // FIXME: This is wrong for "push reg".  "push %bx" should turn into pushw in
 // all modes.  However: "push (addr)" and "push $42" should default to
@@ -2985,6 +2987,8 @@
 def : MnemonicAlias<"pushf",  "pushfq", "att">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushf",  "pushfq", "intel">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushfd", "pushfl", "att">;
+def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In32BitMode]>;
+def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In64BitMode]>;
 
 def : MnemonicAlias<"popad",  "popal",  "intel">, Requires<[Not64BitMode]>;
 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;


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