[llvm] r336247 - [X86][SSE] Add reduced crash test case for r336113 - [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 4 01:55:23 PDT 2018
Author: rksimon
Date: Wed Jul 4 01:55:23 2018
New Revision: 336247
URL: http://llvm.org/viewvc/llvm-project?rev=336247&view=rev
Log:
[X86][SSE] Add reduced crash test case for r336113 - [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values
The patch was reverted at r336189 due to crashes
Modified:
llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll
Modified: llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll?rev=336247&r1=336246&r2=336247&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll Wed Jul 4 01:55:23 2018
@@ -239,3 +239,28 @@ define <8 x i16> @test9(<8 x i16> %a) {
%lshr = ashr <8 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3>
ret <8 x i16> %lshr
}
+
+define <8 x i32> @test10(<8 x i32>* %a) {
+; SSE-LABEL: test10:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa (%rdi), %xmm0
+; SSE-NEXT: movdqa 16(%rdi), %xmm1
+; SSE-NEXT: psrad %xmm0, %xmm1
+; SSE-NEXT: psrad $1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test10:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovdqa (%rdi), %xmm0
+; AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test10:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovdqa (%rdi), %ymm0
+; AVX2-NEXT: vpsrad $1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+ %ld = load <8 x i32>, <8 x i32>* %a, align 32
+ %ashr = ashr <8 x i32> %ld, <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ ret <8 x i32> %ashr
+}
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