[PATCH] D48877: [X86][BtVer2][MCA] Recognize CMPEQ zero-idioms too

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, courbet, andreadb.
Herald added a subscriber: gbedwell.

Commit message of https://reviews.llvm.org/rL334303 said:

  As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and
  Jaguar pipeline - Dependency-breaking instructions), these instructions
  are dependency breaking and fast-path zero the destination register
  (and appropriate EFLAGS bits).

But that very section also listed `PCMPEQx` right before `PCMPGTx` in that very list.
So `CMPEQ` should too be a zero-idiom. (I'm not too use about the MMX version though.)

I'm not seeing anything in the commit messages/the testfile/schedule that would
suggest that `CMPEQ` is omitted intentionally.
So i can only assume it was just not noticed.

Admittedly, i do not have that CPU, so i can not test with `llvm-exegesis` myself.

Found accidentally while continuing trying to look into b**d**ver2 scheduling profile..


Repository:
  rL LLVM

https://reviews.llvm.org/D48877

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/zero-idioms.s

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