[llvm] r336144 - [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.

[Vadzim Dambrouski via llvm-commits]

Author: dambrouski
Date: Mon Jul  2 14:05:26 2018
New Revision: 336144

URL: http://llvm.org/viewvc/llvm-project?rev=336144&view=rev
Log:
[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.

Reviewers: efriedma, rogfer01, javed.absar

Reviewed By: efriedma, rogfer01

Subscribers: kristof.beyls, chrib, llvm-commits

Differential Revision: https://reviews.llvm.org/D48846

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=336144&r1=336143&r2=336144&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jul  2 14:05:26 2018
@@ -4681,9 +4681,11 @@ SDValue ARMTargetLowering::LowerBRCOND(S
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = Cond.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (Cond.getResNo() == 1 &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
+       Opc == ISD::USUBO || OptimizeMul)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
       return SDValue();
@@ -4730,9 +4732,11 @@ SDValue ARMTargetLowering::LowerBR_CC(SD
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = LHS.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+       Opc == ISD::USUBO || OptimizeMul) &&
       (CC == ISD::SETEQ || CC == ISD::SETNE)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))

Modified: llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll?rev=336144&r1=336143&r2=336144&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll Mon Jul  2 14:05:26 2018
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB
 
 define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: sadd:
@@ -81,6 +82,8 @@ define i32 @smul(i32 %a, i32 %b) local_u
 ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-LABEL: smul:
+; CHECK-V6M-THUMB: bl __aeabi_lmul
 entry:
   %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1
@@ -100,6 +103,8 @@ define i32 @umul(i32 %a, i32 %b) local_u
 ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], #0
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-LABEL: umul:
+; CHECK-V6M-THUMB: bl __aeabi_lmul
 entry:
   %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1