[PATCH] D48823: [AArch64][SVE] Asm: Support for FMUL (indexed)

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: rengolin, fhahn, SjoerdMeijer, samparker.
Herald added a reviewer: javed.absar.
Herald added subscribers: rkruppe, kristof.beyls, tschuett.

Unpredicated FP-multiply of SVE vector with a vector-element given by
vector[index], for example:

  fmul z0.s, z1.s, z2.s[0]

which performs an unpredicated FP-multiply of all 32-bit elements in
'z1' with the first element from 'z2'.

This patch adds restricted register classes for SVE vectors:

  ZPR_3b (only z0..z7 are allowed)  - for indexed vector of 16/32-bit elements.
  ZPR_4b (only z0..z15 are allowed) - for indexed vector of 64-bit elements.


https://reviews.llvm.org/D48823

Files:
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  lib/Target/AArch64/SVEInstrFormats.td
  test/MC/AArch64/SVE/fmul-diagnostics.s
  test/MC/AArch64/SVE/fmul.s

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