[llvm] r336090 - [AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 2 02:31:11 PDT 2018
Author: s.desmalen
Date: Mon Jul 2 02:31:11 2018
New Revision: 336090
URL: http://llvm.org/viewvc/llvm-project?rev=336090&view=rev
Log:
[AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.
Increment/decrement vector by multiple of predicate constraint
element count.
The variants added by this patch are:
- INCH, INCW, INC
and (saturating):
- SQINCH, SQINCW, SQINCD
- UQINCH, UQINCW, UQINCW
- SQDECH, SQINCW, SQINCD
- UQDECH, UQINCW, UQINCW
For example:
incw z0.s, all, mul #4
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incd.s
llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/inch.s
llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incw.s
llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdech.s
llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincd.s
llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqinch.s
llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincw.s
llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdech.s
llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincd.s
llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqinch.s
llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincw.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Jul 2 02:31:11 2018
@@ -574,6 +574,25 @@ let Predicates = [HasSVE] in {
defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
+ defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>;
+ defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>;
+ defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>;
+ defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>;
+ defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>;
+ defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>;
+ defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>;
+ defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>;
+ defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>;
+ defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>;
+ defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>;
+ defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>;
+ defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>;
+ defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>;
+ defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>;
+ defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>;
+ defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>;
+ defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>;
+
defm INDEX_RR : sve_int_index_rr<"index">;
defm INDEX_IR : sve_int_index_ir<"index">;
defm INDEX_RI : sve_int_index_ri<"index">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Jul 2 02:31:11 2018
@@ -285,6 +285,36 @@ let Predicates = [HasSVE] in {
// SVE Element Count Group
//===----------------------------------------------------------------------===//
+class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
+ asm, "\t$Zdn, $pattern, mul $imm4",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zdn;
+ bits<5> pattern;
+ bits<4> imm4;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = opc{4-3};
+ let Inst{21} = 0b1;
+ let Inst{20} = opc{2};
+ let Inst{19-16} = imm4;
+ let Inst{15-12} = 0b1100;
+ let Inst{11-10} = opc{1-0};
+ let Inst{9-5} = pattern;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
+ def NAME : sve_int_countvlv<opc, asm, zprty>;
+
+ def : InstAlias<asm # "\t$Zdn, $pattern",
+ (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
+ def : InstAlias<asm # "\t$Zdn",
+ (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
+}
+
class sve_int_pred_pattern_a<bits<3> opc, string asm>
: I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
asm, "\t$Rdn, $pattern, mul $imm4",
Modified: llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incb-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,12 @@ incb sp
// CHECK-NEXT: incb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// INCB does not have a vector equivalent
+incb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.
Modified: llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incd-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,12 @@ incd sp
// CHECK-NEXT: incd sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// incd requires z0.d
+incd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: incd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.
Modified: llvm/trunk/test/MC/AArch64/SVE/incd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incd.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incd.s Mon Jul 2 02:31:11 2018
@@ -7,6 +7,39 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+incd z0.d
+// CHECK-INST: incd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd z0.d, all
+// CHECK-INST: incd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd z0.d, all, mul #1
+// CHECK-INST: incd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd z0.d, all, mul #16
+// CHECK-INST: incd z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
incd x0
// CHECK-INST: incd x0
// CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
@@ -31,6 +64,11 @@ incd x0, all, mul #16
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e3 ff 04 <unknown>
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
incd x0, pow2
// CHECK-INST: incd x0, pow2
// CHECK-ENCODING: [0x00,0xe0,0xf0,0x04]
Modified: llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/inch-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,12 @@ inch sp
// CHECK-NEXT: inch sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// inch requires z0.h
+inch z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: inch z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.
Modified: llvm/trunk/test/MC/AArch64/SVE/inch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/inch.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/inch.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/inch.s Mon Jul 2 02:31:11 2018
@@ -7,6 +7,39 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+inch z0.h
+// CHECK-INST: inch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch z0.h, all
+// CHECK-INST: inch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch z0.h, all, mul #1
+// CHECK-INST: inch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch z0.h, all, mul #16
+// CHECK-INST: inch z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
inch x0
// CHECK-INST: inch x0
// CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
@@ -31,6 +64,11 @@ inch x0, all, mul #16
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e3 7f 04 <unknown>
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
inch x0, pow2
// CHECK-INST: inch x0, pow2
// CHECK-ENCODING: [0x00,0xe0,0x70,0x04]
Modified: llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incw-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,12 @@ incw sp
// CHECK-NEXT: incw sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+// incw requires z0.s
+incw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: incw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.
Modified: llvm/trunk/test/MC/AArch64/SVE/incw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incw.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incw.s Mon Jul 2 02:31:11 2018
@@ -7,6 +7,39 @@
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+incw z0.s
+// CHECK-INST: incw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw z0.s, all
+// CHECK-INST: incw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw z0.s, all, mul #1
+// CHECK-INST: incw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw z0.s, all, mul #16
+// CHECK-INST: incw z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
incw x0
// CHECK-INST: incw x0
// CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
@@ -31,6 +64,12 @@ incw x0, all, mul #16
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 e3 bf 04 <unknown>
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
+
incw x0, pow2
// CHECK-INST: incw x0, pow2
// CHECK-ENCODING: [0x00,0xe0,0xb0,0x04]
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecb-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqdecb sp
// CHECK-NEXT: sqdecb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdecb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecd-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqdecd sp
// CHECK-NEXT: sqdecd sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqdecd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqdecd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecd.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecd.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqdecd x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqdecd z0.d
+// CHECK-INST: sqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd z0.d, all
+// CHECK-INST: sqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd z0.d, all, mul #1
+// CHECK-INST: sqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd z0.d, all, mul #16
+// CHECK-INST: sqdecd z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcb,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb ef 04 <unknown>
+
+sqdecd z0.d, pow2
+// CHECK-INST: sqdecd z0.d, pow2
+// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>
+
+sqdecd z0.d, pow2, mul #16
+// CHECK-INST: sqdecd z0.d, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdech-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqdech sp
// CHECK-NEXT: sqdech sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdech z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqdech z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdech.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdech.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdech.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdech.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqdech x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqdech z0.h
+// CHECK-INST: sqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+
+sqdech z0.h, all
+// CHECK-INST: sqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+
+sqdech z0.h, all, mul #1
+// CHECK-INST: sqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+
+sqdech z0.h, all, mul #16
+// CHECK-INST: sqdech z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcb,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb 6f 04 <unknown>
+
+sqdech z0.h, pow2
+// CHECK-INST: sqdech z0.h, pow2
+// CHECK-ENCODING: [0x00,0xc8,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 60 04 <unknown>
+
+sqdech z0.h, pow2, mul #16
+// CHECK-INST: sqdech z0.h, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc8,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecw-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqdecw sp
// CHECK-NEXT: sqdecw sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdecw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqdecw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecw.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecw.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqdecw x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqdecw z0.s
+// CHECK-INST: sqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+
+sqdecw z0.s, all
+// CHECK-INST: sqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+
+sqdecw z0.s, all, mul #1
+// CHECK-INST: sqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+
+sqdecw z0.s, all, mul #16
+// CHECK-INST: sqdecw z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcb,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb af 04 <unknown>
+
+sqdecw z0.s, pow2
+// CHECK-INST: sqdecw z0.s, pow2
+// CHECK-ENCODING: [0x00,0xc8,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 a0 04 <unknown>
+
+sqdecw z0.s, pow2, mul #16
+// CHECK-INST: sqdecw z0.s, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc8,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincb-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqincb sp
// CHECK-NEXT: sqincb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqincb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqincb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincd-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqincd sp
// CHECK-NEXT: sqincd sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqincd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqincd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincd.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincd.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqincd x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqincd z0.d
+// CHECK-INST: sqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+
+sqincd z0.d, all
+// CHECK-INST: sqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+
+sqincd z0.d, all, mul #1
+// CHECK-INST: sqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+
+sqincd z0.d, all, mul #16
+// CHECK-INST: sqincd z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 ef 04 <unknown>
+
+sqincd z0.d, pow2
+// CHECK-INST: sqincd z0.d, pow2
+// CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 e0 04 <unknown>
+
+sqincd z0.d, pow2, mul #16
+// CHECK-INST: sqincd z0.d, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqinch-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqinch sp
// CHECK-NEXT: sqinch sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqinch z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqinch z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqinch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqinch.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqinch.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqinch.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqinch x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqinch z0.h
+// CHECK-INST: sqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+
+sqinch z0.h, all
+// CHECK-INST: sqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+
+sqinch z0.h, all, mul #1
+// CHECK-INST: sqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+
+sqinch z0.h, all, mul #16
+// CHECK-INST: sqinch z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 6f 04 <unknown>
+
+sqinch z0.h, pow2
+// CHECK-INST: sqinch z0.h, pow2
+// CHECK-ENCODING: [0x00,0xc0,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 60 04 <unknown>
+
+sqinch z0.h, pow2, mul #16
+// CHECK-INST: sqinch z0.h, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc0,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincw-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -18,6 +18,11 @@ sqincw sp
// CHECK-NEXT: sqincw sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqincw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqincw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincw.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincw.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ sqincw x0, w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqincw z0.s
+// CHECK-INST: sqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+
+sqincw z0.s, all
+// CHECK-INST: sqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+
+sqincw z0.s, all, mul #1
+// CHECK-INST: sqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+
+sqincw z0.s, all, mul #16
+// CHECK-INST: sqincw z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 af 04 <unknown>
+
+sqincw z0.s, pow2
+// CHECK-INST: sqincw z0.s, pow2
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>
+
+sqincw z0.s, pow2, mul #16
+// CHECK-INST: sqincw z0.s, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecb-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqdecb sp
// CHECK-NEXT: uqdecb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqdecb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqdecb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned dec only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecd-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqdecd sp
// CHECK-NEXT: uqdecd sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqdecd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqdecd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned dec only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecd.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecd.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ uqdecd w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+uqdecd z0.d
+// CHECK-INST: uqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+
+uqdecd z0.d, all
+// CHECK-INST: uqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+
+uqdecd z0.d, all, mul #1
+// CHECK-INST: uqdecd z0.d
+// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+
+uqdecd z0.d, all, mul #16
+// CHECK-INST: uqdecd z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcf,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf ef 04 <unknown>
+
+uqdecd z0.d, pow2
+// CHECK-INST: uqdecd z0.d, pow2
+// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc e0 04 <unknown>
+
+uqdecd z0.d, pow2, mul #16
+// CHECK-INST: uqdecd z0.d, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdech-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqdech sp
// CHECK-NEXT: uqdech sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqdech z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqdech z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned dec only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdech.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdech.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdech.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdech.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ uqdech w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+uqdech z0.h
+// CHECK-INST: uqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+
+uqdech z0.h, all
+// CHECK-INST: uqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+
+uqdech z0.h, all, mul #1
+// CHECK-INST: uqdech z0.h
+// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+
+uqdech z0.h, all, mul #16
+// CHECK-INST: uqdech z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcf,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf 6f 04 <unknown>
+
+uqdech z0.h, pow2
+// CHECK-INST: uqdech z0.h, pow2
+// CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc 60 04 <unknown>
+
+uqdech z0.h, pow2, mul #16
+// CHECK-INST: uqdech z0.h, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecw-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqdecw sp
// CHECK-NEXT: uqdecw sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqdecw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqdecw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned dec only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecw.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecw.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ uqdecw w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+uqdecw z0.s
+// CHECK-INST: uqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+
+uqdecw z0.s, all
+// CHECK-INST: uqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+
+uqdecw z0.s, all, mul #1
+// CHECK-INST: uqdecw z0.s
+// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+
+uqdecw z0.s, all, mul #16
+// CHECK-INST: uqdecw z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcf,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cf af 04 <unknown>
+
+uqdecw z0.s, pow2
+// CHECK-INST: uqdecw z0.s, pow2
+// CHECK-ENCODING: [0x00,0xcc,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc a0 04 <unknown>
+
+uqdecw z0.s, pow2, mul #16
+// CHECK-INST: uqdecw z0.s, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xcc,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 cc af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincb-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqincb sp
// CHECK-NEXT: uqincb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqincb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: uqincb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned inc only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincd-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqincd sp
// CHECK-NEXT: uqincd sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqincd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqincd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned inc only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincd.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincd.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincd.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ uqincd w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+uqincd z0.d
+// CHECK-INST: uqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+
+uqincd z0.d, all
+// CHECK-INST: uqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+
+uqincd z0.d, all, mul #1
+// CHECK-INST: uqincd z0.d
+// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+
+uqincd z0.d, all, mul #16
+// CHECK-INST: uqincd z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc7,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 ef 04 <unknown>
+
+uqincd z0.d, pow2
+// CHECK-INST: uqincd z0.d, pow2
+// CHECK-ENCODING: [0x00,0xc4,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 e0 04 <unknown>
+
+uqincd z0.d, pow2, mul #16
+// CHECK-INST: uqincd z0.d, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc4,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 ef 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqinch-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqinch sp
// CHECK-NEXT: uqinch sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqinch z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqinch z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned inc only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqinch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqinch.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqinch.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqinch.s Mon Jul 2 02:31:11 2018
@@ -11,6 +11,7 @@
// ---------------------------------------------------------------------------//
// Test 64-bit form (x0) and its aliases
// ---------------------------------------------------------------------------//
+
uqinch x0
// CHECK-INST: uqinch x0
// CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
@@ -78,6 +79,47 @@ uqinch w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+uqinch z0.h
+// CHECK-INST: uqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+
+uqinch z0.h, all
+// CHECK-INST: uqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+
+uqinch z0.h, all, mul #1
+// CHECK-INST: uqinch z0.h
+// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+
+uqinch z0.h, all, mul #16
+// CHECK-INST: uqinch z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc7,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 6f 04 <unknown>
+
+uqinch z0.h, pow2
+// CHECK-INST: uqinch z0.h, pow2
+// CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 60 04 <unknown>
+
+uqinch z0.h, pow2, mul #16
+// CHECK-INST: uqinch z0.h, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 6f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincw-diagnostics.s Mon Jul 2 02:31:11 2018
@@ -13,6 +13,11 @@ uqincw sp
// CHECK-NEXT: uqincw sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqincw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqincw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Operands not matching up (unsigned inc only has one register operand)
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincw.s?rev=336090&r1=336089&r2=336090&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincw.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincw.s Mon Jul 2 02:31:11 2018
@@ -78,6 +78,46 @@ uqincw w0, pow2, mul #16
// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+uqincw z0.s
+// CHECK-INST: uqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+
+uqincw z0.s, all
+// CHECK-INST: uqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+
+uqincw z0.s, all, mul #1
+// CHECK-INST: uqincw z0.s
+// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+
+uqincw z0.s, all, mul #16
+// CHECK-INST: uqincw z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc7,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c7 af 04 <unknown>
+
+uqincw z0.s, pow2
+// CHECK-INST: uqincw z0.s, pow2
+// CHECK-ENCODING: [0x00,0xc4,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 a0 04 <unknown>
+
+uqincw z0.s, pow2, mul #16
+// CHECK-INST: uqincw z0.s, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc4,0xaf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c4 af 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//
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