[llvm] r336076 - [llvm-exegesis][NFC] Cleanup useless braces.

[Clement Courbet via llvm-commits]

Author: courbet
Date: Sun Jul  1 23:39:55 2018
New Revision: 336076

URL: http://llvm.org/viewvc/llvm-project?rev=336076&view=rev
Log:
[llvm-exegesis][NFC] Cleanup useless braces.

Modified:
    llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

Modified: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp?rev=336076&r1=336075&r2=336076&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp Sun Jul  1 23:39:55 2018
@@ -132,32 +132,24 @@ class ExegesisX86Target : public Exegesi
 
   std::vector<llvm::MCInst>
   setRegToConstant(unsigned Reg) const override {
-    if (llvm::X86::GR8RegClass.contains(Reg)) {
+    if (llvm::X86::GR8RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR16RegClass.contains(Reg)) {
+    if (llvm::X86::GR16RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR32RegClass.contains(Reg)) {
+    if (llvm::X86::GR32RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::GR64RegClass.contains(Reg)) {
+    if (llvm::X86::GR64RegClass.contains(Reg))
       return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)};
-    }
-    if (llvm::X86::VR128XRegClass.contains(Reg)) {
+    if (llvm::X86::VR128XRegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm);
-    }
-    if (llvm::X86::VR256XRegClass.contains(Reg)) {
+    if (llvm::X86::VR256XRegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQUYrm);
-    }
-    if (llvm::X86::VR512RegClass.contains(Reg)) {
+    if (llvm::X86::VR512RegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm);
-    }
     if (llvm::X86::RFP32RegClass.contains(Reg) ||
         llvm::X86::RFP64RegClass.contains(Reg) ||
-        llvm::X86::RFP80RegClass.contains(Reg)) {
+        llvm::X86::RFP80RegClass.contains(Reg))
       return setVectorRegToConstant(Reg, 8, llvm::X86::LD_Fp64m);
-    }
     return {};
   }