[PATCH] D47999: MIR YAML TracksRegLiveness default to true in yaml parser

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi updated this revision to Diff 153633.
plotfi added a comment.

I've updated this to a much simpler diff. I think instead of changing when we set this stuff in the MachineIntrs before regalloc maybe the simplest thing to do is make it so that absence of "tracksRegLiveness" in the MIR Yaml section implies "tracksRegLiveness: true" @MatzeB What do you think?


https://reviews.llvm.org/D47999

Files:
  include/llvm/CodeGen/MIRYamlMapping.h
  test/CodeGen/MIR/X86/force-liveness-track.mir


Index: test/CodeGen/MIR/X86/force-liveness-track.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/X86/force-liveness-track.mir
@@ -0,0 +1,13 @@
+# RUN: llc -o - %s -mtriple=x86_64 | FileCheck %s
+---
+# CHECK: xorl  %eax, %eax
+# CHECK: movl  %eax, (%rcx)
+# CHECK: retq
+name: func0
+body: |
+  bb.0:
+    %0 : gr32 = MOV32r0 implicit-def $eflags
+    dead %1 : gr32 = COPY %0
+    MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
+    RETQ undef $eax
+...
Index: include/llvm/CodeGen/MIRYamlMapping.h
===================================================================
--- include/llvm/CodeGen/MIRYamlMapping.h
+++ include/llvm/CodeGen/MIRYamlMapping.h
@@ -511,7 +511,7 @@
     YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false);
     YamlIO.mapOptional("selected", MF.Selected, false);
     YamlIO.mapOptional("failedISel", MF.FailedISel, false);
-    YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
+    YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, true);
     YamlIO.mapOptional("registers", MF.VirtualRegisters,
                        std::vector<VirtualRegisterDefinition>());
     YamlIO.mapOptional("liveins", MF.LiveIns,


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