[PATCH] D48692: [WebAssembly] Update comments for non-splat pow2 vector test case

[Heejin Ahn via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL336018: [WebAssembly] Update comments for non-splat pow2 vector test case (authored by aheejin, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D48692?vs=153405&id=153577#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48692

Files:
  llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll
  llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll


Index: llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll
===================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-elf"
+
+; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
+; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
+; entry we don't need a shr).
+
+; CHECK-LABEL: vector_sdiv:
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.shr_u
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.shr_u
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.shr_u
+; CHECK-DAG:  i32.store
+define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %y, align 16
+  %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
+  store <4 x i32> %div, <4 x i32>* %x, align 16
+  ret void
+}
Index: llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll
===================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll
@@ -1,22 +0,0 @@
-; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-
-target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown-elf"
-
-; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
-
-; CHECK-LABEL: vector_sdiv:
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
-entry:
-  %0 = load <4 x i32>, <4 x i32>* %y, align 16
-  %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
-  store <4 x i32> %div, <4 x i32>* %x, align 16
-  ret void
-}


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