[llvm] r336018 - [WebAssembly] Update comments for non-splat pow2 vector test case

[Heejin Ahn via llvm-commits]

Author: aheejin
Date: Fri Jun 29 14:27:20 2018
New Revision: 336018

URL: http://llvm.org/viewvc/llvm-project?rev=336018&view=rev
Log:
[WebAssembly] Update comments for non-splat pow2 vector test case

Summary:
After rL335727, (sdiv X, 1) is treated as a special case, so we can
safely transform 'sdiv's in non-splat pow vectors into 'shr's even when
some of its entries are '1'. The test expectations have been already
fixed in rL335771, but the comments were out of date.

Also changed the filename from `vector_sdiv.ll` to `vector-sdiv.ll` to
be consistent with other test file names.

Reviewers: RKSimon

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D48692

Added:
    llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll
      - copied, changed from r336015, llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll
Removed:
    llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll

Copied: llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll (from r336015, llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll?p2=llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll&p1=llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll&r1=336015&r2=336018&rev=336018&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/vector-sdiv.ll Fri Jun 29 14:27:20 2018
@@ -3,7 +3,9 @@
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown-elf"
 
-; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
+; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
+; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
+; entry we don't need a shr).
 
 ; CHECK-LABEL: vector_sdiv:
 ; CHECK-DAG:  i32.store

Removed: llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll?rev=336017&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/vector_sdiv.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-
-target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown-elf"
-
-; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
-
-; CHECK-LABEL: vector_sdiv:
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-; CHECK-DAG:  i32.shr_u
-; CHECK-DAG:  i32.store
-define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
-entry:
-  %0 = load <4 x i32>, <4 x i32>* %y, align 16
-  %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
-  store <4 x i32> %div, <4 x i32>* %x, align 16
-  ret void
-}