[PATCH] D48725: [SLP] Vectorize bit-parallel operations with SWAR.

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 29 13:01:23 PDT 2018


efriedma added a comment.

Currently, SLPVectorizer does not generate vector types smaller than TargetTransformInfo::getMinVectorRegisterBitWidth().  This is 128 on many targets, including x86.  But that doesn't really make sense, in general; even if a target doesn't have 64-bit vector registers, it can emulate them using 128-bit vector registers.  The loop vectorizer frequently takes advantage of this; the SLP vectorizer should also take advantage of this, independent of anything else.

There's also the possibility of emitting "vector" operations using GPRs.  This generally makes sense; it's basically the same transform even if the available instructions are more limited.  But this patch doesn't really do that: it emits IR operations using vector types.  SelectionDAG legalization will generally prefer to emit vector operations to vector registers, if they're available, or just scalarize if there aren't any vector registers.  There's basically one exception to that rule, which you've stumbled across; DAGCombine will transform a vector or float load+store into an integer load+store, if the loaded value doesn't have any other uses.  But we shouldn't rely on that, I think; if we're doing cost modeling based on the cost of integer operations, we should explicitly emit integer operations in IR.


Repository:
  rL LLVM

https://reviews.llvm.org/D48725





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