[PATCH] D48772: [AMDGPU] Add VALU to V_INTERP Instructions

[Ryan Taylor via Phabricator via llvm-commits]

rtaylor created this revision.
Herald added subscribers: llvm-commits, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

Wait states are not properly being inserted after buffer_store for v_interp instructions.

Add VALU to V_INTERP instructions so that the GCNHazardRecognizer can
check and insert the appropriate wait states when needed.

Change-Id: I3da47a7889a5fd98a4c5ecf02b806e9b9faa16b3


Repository:
  rL LLVM

https://reviews.llvm.org/D48772

Files:
  lib/Target/AMDGPU/SIInstructions.td
  test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir


Index: test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
@@ -0,0 +1,19 @@
+# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+
+# GCN-LABEL: name: hazard_buffer_store_v_interp
+# GCN:    bb.0.entry:
+# GCN:    BUFFER_STORE_DWORDX4_OFFSET_exact
+# GCN:    S_NOP
+# GCN:    V_INTERP_P1_F32
+
+name:            hazard_buffer_store_v_interp
+body:             |
+  bb.0.entry:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
+  
+    BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
+    $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
+    S_ENDPGM
+
+...
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -36,7 +36,7 @@
 // Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI)
 def VINTRPDst : VINTRPDstOperand <VGPR_32>;
 
-let Uses = [M0, EXEC] in {
+let Uses = [M0, EXEC], VALU = 1 in {
 
 // FIXME: Specify SchedRW for VINTRP insturctions.
 
@@ -81,7 +81,8 @@
   [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan),
                                      (i32 imm:$attr)))]>;
 
-} // End Uses = [M0, EXEC]
+
+} // End Uses = [M0, EXEC], VALU = 1
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions


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