[PATCH] D48725: [SLP] Vectorize bit-parallel operations with SWAR.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

If we're only ever going to be using load/store + and/or/xor ops I wonder if we'd be better off doing this in the DAG alongside the LoadCombine handling? SLP is going to struggle with more general cases where the sizes of bundle elements differ.

My main interest in SWAR patterns was mainly for bitfield arithmetic cases such as PR34526 which I figured we could perform in InstCombine with some suitable overflow/demandedbits magic


Repository:
  rL LLVM

https://reviews.llvm.org/D48725