[PATCH] D48614: [SelectionDAG] Fix promotion of extracted FP vector element

[Bryan Chan via Phabricator via llvm-commits]

bryanpkc created this revision.
bryanpkc added reviewers: RKSimon, bogner.
Herald added a subscriber: llvm-commits.

https://reviews.llvm.org/D32391 added support for extension/truncation for both integer and float types,
but the handling of ISD::EXTRACT_VECTOR_ELT still did not expect FP vectors,
leading to an assertion failure in the test case when compiling at -O0.


Repository:
  rL LLVM

https://reviews.llvm.org/D48614

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/X86/pr31088.ll


Index: test/CodeGen/X86/pr31088.ll
===================================================================
--- test/CodeGen/X86/pr31088.ll
+++ test/CodeGen/X86/pr31088.ll
@@ -2,6 +2,7 @@
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+f16c | FileCheck %s --check-prefix=F16C
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+f16c -O0 | FileCheck %s --check-prefix=F16C-O0
 
 define <1 x half> @ir_fadd_v1f16(<1 x half> %arg0, <1 x half> %arg1) nounwind {
 ; X86-LABEL: ir_fadd_v1f16:
@@ -56,6 +57,19 @@
 ; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
 ; F16C-NEXT:    vaddss %xmm1, %xmm0, %xmm0
 ; F16C-NEXT:    retq
+;
+; F16C-O0-LABEL: ir_fadd_v1f16:
+; F16C-O0:       # %bb.0:
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm1, %xmm1
+; F16C-O0-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-O0-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm1, %xmm1
+; F16C-O0-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-O0-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-O0-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; F16C-O0-NEXT:    retq
   %retval = fadd <1 x half> %arg0, %arg1
   ret <1 x half> %retval
 }
@@ -157,6 +171,20 @@
 ; F16C-NEXT:    vaddss %xmm2, %xmm0, %xmm0
 ; F16C-NEXT:    vaddss %xmm3, %xmm1, %xmm1
 ; F16C-NEXT:    retq
+;
+; F16C-O0-LABEL: ir_fadd_v2f16:
+; F16C-O0:       # %bb.0:
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm2, %xmm2
+; F16C-O0-NEXT:    vcvtph2ps %xmm2, %xmm2
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-O0-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-O0-NEXT:    vaddss %xmm2, %xmm0, %xmm0
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm3, %xmm2
+; F16C-O0-NEXT:    vcvtph2ps %xmm2, %xmm2
+; F16C-O0-NEXT:    vcvtps2ph $4, %xmm1, %xmm1
+; F16C-O0-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-O0-NEXT:    vaddss %xmm2, %xmm1, %xmm1
+; F16C-O0-NEXT:    retq
   %retval = fadd <2 x half> %arg0, %arg1
   ret <2 x half> %retval
 }
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4592,7 +4592,8 @@
         // If the vector element type is not legal, the BUILD_VECTOR operands
         // are promoted and implicitly truncated, and the result implicitly
         // extended. Make that explicit here.
-        Elt = getAnyExtOrTrunc(Elt, DL, VT);
+        Elt = VT.isFloatingPoint() ? getFPExtendOrRound(Elt, DL, VT)
+                                   : getAnyExtOrTrunc(Elt, DL, VT);
 
       return Elt;
     }


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